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dc.contributor.author박성주-
dc.date.accessioned2020-09-29T00:11:15Z-
dc.date.available2020-09-29T00:11:15Z-
dc.date.issued2005-07-
dc.identifier.citation전자공학회논문지 SD편, v.42, No.7, Page.37-44en_US
dc.identifier.issn1229-6368-
dc.identifier.urihttps://www.dbpia.co.kr/journal/articleDetail?nodeId=NODE00609639-
dc.identifier.urihttps://repository.hanyang.ac.kr/handle/20.500.11754/154228-
dc.description.abstracthis paper presents effective test patterns and their BIST implementations for SoC and Board interconnects. Initially '6n' algorithm, where ,n, is the total number of interconnect nets, is introduced to completely detect and diagnose both static and crosstalk faults. Then, more economic 'An+V algorithm is described to perfectly capture the crosstalk faults for the interconnect nets separated within a certain distance. It will be shown that both algorithms can be easily implemented as interconnect BIST hardwares with small area penalty than conventional LFSRen_US
dc.language.isoen_USen_US
dc.publisher대한전자공학회en_US
dc.subjectinterconnect testingen_US
dc.subjectcrosstalk faultsen_US
dc.subjecttest pattern generatoren_US
dc.subjectBISTen_US
dc.subjectSoCen_US
dc.subjectstatic faultsen_US
dc.titleCrosstalk과 정적 고장을 고려한 효과적인 연결선 테스트 알고리즘 및 BIST 구현en_US
dc.title.alternativeEfficient Interconnect Test Patterns and BIST Implementation for Crosstalk and Static Faultsen_US
dc.typeArticleen_US
dc.contributor.googleauthor민병우-
dc.contributor.googleauthor이현빈-
dc.contributor.googleauthor송재훈-
dc.contributor.googleauthor박성주-
dc.sector.campusE-
dc.sector.daehakCOLLEGE OF COMPUTING[E]-
dc.sector.departmentDIVISION OF COMPUTER SCIENCE-
dc.identifier.pidpaksj-
Appears in Collections:
COLLEGE OF COMPUTING[E](소프트웨어융합대학) > COMPUTER SCIENCE(소프트웨어학부) > Articles
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