Vertical channel NAND flash memory 구조의 simulation modeling 최적화 및 성능 향상을 위한 개선 구조의 특성 분석에 관한 연구

Abstract

최근 연구되고 있는 3-D memory는 기존 2-D 구조의 scale down 따른 전기적, 공정적, 신뢰성적인 한계를 3-D 구조를 도입하는 것으로서 scale down 없이 집적도 향상이 가능한 우수한 구조로 각광받고 있다. 이중 BICS(Bit-Cost Scalable), P-BICS(Pipe-shaped Bit Cost Scalable), TCAT(Terabit Cell Array Transistor) 구조의 경우 vertical channel 구조를 사용하는 것으로서 lithography step을 대폭적으로 감소시켜서 집적도 향상을 보여주었다.

이러한3-D NAND flash memory 구조는 기존 2-D 구조의 한계를 극복할 새로운 구조로 각광받고 있다. 하지만 연구가 계속 진행되면서 3-D 구조 또한 다수의 문제점을 가지고 있는 것이 밝혀지고 있다.

먼저 제기된 문제점은 역시 nano scale로 소자를 제조할 경우에 2-D와 동일한 문제가 발생하는 점이라고 할 수 있다. 하지만 이 문제들이 3-D에서 더 심각한 것은 2-D에서는 쉽게 공정적 접근을 통해서 해결이 가능한 문제들도 3-D 에서는 그 구조상 사용하기 어렵게 된다는 점이다.

다음으로 제기된 문제점은 channel material인 polysilicon 이라고 할 수 있다. 종래 flash memory 소자들은 모두 거의 결점이 존재하지 않는 crystal silicon 의 이차원 평면상에 제작 되었다. 하지만 3차원 집적 가능한 NAND 플래시 메모리는 증착공정이 가능한 polysilicon 을 채널 물질로 이용한다. polysilicon은 박막내의 수많은 결점으로 인하여 crystal silicon 에 비해 특성이 불안정하며 또한 균일하고 우수한 oxide layer를 만들어 내는데 어려움이 존재한다. 이러한 문제들에 대해서 현재로서는 3-D 구조상 공정적 접근이 어렵기 때문에 필연적으로 소자 구조에서 이러한 문제점을 해결할 추가적인 장치가 필요하게 된다.

이러한 문제점들을 해결하기 위해서 본 논문에서는 SSCG(Sub-Side-Control-Gate) 와 분리되어 있는 charge nitride layer 를 구조상 특징으로 하는 DSCG(Double-Side-Control-Gate) 구조를 제안하였다. 이 제안된 구조는 Synopsys 사의 sentaurus TCAD simulation tool 에 의해서 simulation 되고 평가되었다. 그리고 그 결과 본 논문에서는 SSCG의 동작에 의한 memory performance 개선 효과와 더불어 분리된 charge nitride layer 에 의한 interference effect 감소 효과를 확인하였다.

DSCG의 우수성을 확인하기 위해서 먼저 ideal state 에서의 memory performance 를 BiCS structure와 비교하였다. 이를 위해서 simulation structure를 이후 발전된 process technology 에 의한 short channel device(under 10 nm)까지 고려하기 위해서 이를 위한 production process 에서 일반적인 vertical channel structure와 DSCG에서 각각 고려되어야 할 사항을 확인하였고. 이어서 이를 바탕으로 design 된 structure를 통해서 BiCS 와 ideal state 에서의 memory performance 를 비교하였다.

다음으로는 Simulation results and discussions of memory performance 에서 입증한 memory performance 에 이어서 3 bit multi cell 에서의 cell to cell interference 의 정도와 이를 DSCG를 적용할 경우 그 개선 정도를 정량적으로 분석하였다. 분석에는 각각 SONOS, MONOS structure별로 그 특성을 비교하고 나아가서 DSCG의 적용에 따른 effect를 BiCS가 만족하기 위해서는 감수해야 할 CTCD, pass voltage 등을 산출해서 이것을 바탕으로 DSCG를 적용했을 경우 얻을 수 있는 이득을 산출하였다. 마지막으로 이를 통해서 최종적으로 DSCG structure 가 가지는 advantage를 정량적으로 입증하였다. |Recently, three dimensional (3-D) vertical memory structures have become a major field of interest as they are being proposed as solutions that can overcome problems in electrical characteristics, processes, and reliability related to the lateral scale-down in conventional non-volatile memory structures. The 3-D memory structures with nitride charge traps as the charge storage units, such as bit-cost scalable (BiCS) memory, pipeshaped bit cost scalable (P-BiCS) memory, and terabit cell array transistor (TCAT), utilize vertically oriented transport channels, where the gain in integration comes from increasing the number of stacked gate layers rather than decreasing the lateral dimensions of a unit memory cell.

These 3-D NAND flash memory structures have been taking center stage as a new structure for improving limitations in the conventional 2-D structure. However, there are various problems in the 3-D structure according to current ongoing studies on the issue. The primary issue is to present the same problem as the 2-D structure as elements are fabricated as a nano scale. The more serious problem in this case is that the problem in the 2-D structure can easily be solved through an approach to the process but the approach cannot be allowed to the 3-D structure due to its own architectural characteristic.

The secondary issue is in its channel material, polysilicon. The conventional flash memory elements have been fabricated on the surface of the crystal silicon that shows almost no defects. However, the NAND flash memory that can be integrated as a 3-D manner uses polysilicon, which can apply a deposition process, as a channel material. The polysilicon shows unstable characteristics compared to the crystal silicon due to lots of defects in its thin film and difficulties in producing uniform and excellent oxide layers. Because it is difficult to solve these issues through an approach to its process due to the 3-D architectural characteristic, it essentially requires an additional device for solving these issues in the element structure.

To solve these problems, in this thesis, we proposed the ‘Double Side Control Gate’(DSCG) which solves problems the conventional 3-D vertical NAND flash structure using the added Sub-Side-Control-Gate(SSCG) and segregate charge nitride layer. The proposed DSCG structure was simulated and tested by the sentaurus TCAD(Synopsys. Inc) tool and confirmed the improvement of memory performance and the reduction of interference effect.

First, we compared the memory performance of the DSCG structure in an ideal state with that of the BiCS structure in order to prove the superiority of DSCG explained in ‘A proposal of DSCG(Double Side Control Gate).’ For this, we suggested points to be considered in the production process for general vertical channel structures and in DSCG in order to give consideration to short channel devices (under 10 nm) expected to appear with future development of process technologies, and using a structure designed based on the considerations we compared memory performance in an ideal state between DSCG and BiCS.

Second, we analyzed cell-to-cell interference in 3-bit multi-cells along with memory performance proved in ‘Simulation results and discussions of memory performance,’ and made quantitative analysis on the reduction of cell-to-cell interference resulting from the application of DSCG. In the analysis, we compared characteristics for SONOS and MONOS structures, and estimated benefits expected from the application of DSCG by calculating CTCD, pass voltage, etc. for BiCS to sacrifice in order to attain the same effect as that obtained from the application of DSCG. Lastly, we proved the advantages of the DSCG structure quantitatively.; Recently, three dimensional (3-D) vertical memory structures have become a major field of interest as they are being proposed as solutions that can overcome problems in electrical characteristics, processes, and reliability related to the lateral scale-down in conventional non-volatile memory structures. The 3-D memory structures with nitride charge traps as the charge storage units, such as bit-cost scalable (BiCS) memory, pipeshaped bit cost scalable (P-BiCS) memory, and terabit cell array transistor (TCAT), utilize vertically oriented transport channels, where the gain in integration comes from increasing the number of stacked gate layers rather than decreasing the lateral dimensions of a unit memory cell.

These 3-D NAND flash memory structures have been taking center stage as a new structure for improving limitations in the conventional 2-D structure. However, there are various problems in the 3-D structure according to current ongoing studies on the issue. The primary issue is to present the same problem as the 2-D structure as elements are fabricated as a nano scale. The more serious problem in this case is that the problem in the 2-D structure can easily be solved through an approach to the process but the approach cannot be allowed to the 3-D structure due to its own architectural characteristic.

The secondary issue is in its channel material, polysilicon. The conventional flash memory elements have been fabricated on the surface of the crystal silicon that shows almost no defects. However, the NAND flash memory that can be integrated as a 3-D manner uses polysilicon, which can apply a deposition process, as a channel material. The polysilicon shows unstable characteristics compared to the crystal silicon due to lots of defects in its thin film and difficulties in producing uniform and excellent oxide layers. Because it is difficult to solve these issues through an approach to its process due to the 3-D architectural characteristic, it essentially requires an additional device for solving these issues in the element structure.

To solve these problems, in this thesis, we proposed the ‘Double Side Control Gate’(DSCG) which solves problems the conventional 3-D vertical NAND flash structure using the added Sub-Side-Control-Gate(SSCG) and segregate charge nitride layer. The proposed DSCG structure was simulated and tested by the sentaurus TCAD(Synopsys. Inc) tool and confirmed the improvement of memory performance and the reduction of interference effect.

First, we compared the memory performance of the DSCG structure in an ideal state with that of the BiCS structure in order to prove the superiority of DSCG explained in ‘A proposal of DSCG(Double Side Control Gate).’ For this, we suggested points to be considered in the production process for general vertical channel structures and in DSCG in order to give consideration to short channel devices (under 10 nm) expected to appear with future development of process technologies, and using a structure designed based on the considerations we compared memory performance in an ideal state between DSCG and BiCS.

Second, we analyzed cell-to-cell interference in 3-bit multi-cells along with memory performance proved in ‘Simulation results and discussions of memory performance,’ and made quantitative analysis on the reduction of cell-to-cell interference resulting from the application of DSCG. In the analysis, we compared characteristics for SONOS and MONOS structures, and estimated benefits expected from the application of DSCG by calculating CTCD, pass voltage, etc. for BiCS to sacrifice in order to attain the same effect as that obtained from the application of DSCG. Lastly, we proved the advantages of the DSCG structure quantitatively.