Low-Power and Small-Area DC Voltage Generators based on External Power for NAND Flash Memory

Abstract

NAND flash memories based solid-state drives (SSDs) are rapidly expanding into the storage markets formerly dominated by hard disk drives (HDDs), and are used in numerous applications. To satisfy strict enterprise application requirements and future storage system demands, it is necessary to develop faster, reliable, energy-efficient, and area-efficient SSDs. SSDs consist of NAND flash memories, DRAM, and an integrated controller. Traditional memory cell scaling is running into hard limits due to quadruple patterning and extreme ultraviolet lithography, motivating which has motivated the development of the next-generation node beyond the 16 nm-class NAND flash, so alternative approaches are being investigated. A main approach is reducing the peripheral circuit area of NAND flash memory with low-power operation. In conventional peripheral design, each NAND chip has a charge pump as a program-voltage generator and LDO as an internal-voltage generator. As the supply voltage (VDD) is decreased for low-power operation, the number of charge pump stages increases, so the total area of charge-pump more than doubles, which increases the NAND flash chip area by 5 % to 10 %. The output ripple program voltage degrades the reliability of NAND flash memory, and causes over-programming operation. Therefore, a low-ripple high voltage regulator with a small area is required to improve read/write performance. The unacceptably large current flows to charge a huge bit-line capacitance. To keep the every bit-line constant, a robust internal power source is needed. To guarantee robust internal power, a conventional low drop-out (LDO) regulator needs more output capacitance; therefore, an LDO regulator with a larger area. To overcome these drawbacks and improve area efficiency, output capacitor-less LDO regulator has become a topic of intense interest. The main challenge in the design of capacitor-less LDO, the main issue is to minimize the quiescent current and dropout voltage while maintaining good regulation and a fast response time. First, to improve power and area efficiency without breakdown, we reduced the charge pump stage using external high voltages of 12 V and 5 V with a proposed soft pre-charge high-voltage switch. Second, to reduce the ripple voltage of the H/V linear regulator, we proposed an additional feedback technique. Finally, to increase sensing accuracy in the sensing phase, a robust internal voltage source with a small area is key, so the ultra fast capacitor-less internal voltage regulator known a LDO regulator is proposed. The proposed scheme was implemented in a standard high-voltage CMOS process. The measurement results show the best figure of the merits (FOM) in recently published papers.