Robust Low Power CMOS Design for Memory and Interface Circuits

Abstract

Static random-access memory (SRAM) is the most widely used digital macro, and the level shifter circuits are a necessary part of modern multi-supply SoCs. Low-power operation is of key importance as many emerging applications like remote wireless-sensor-nodes, on-body networks, biomedical applications and mobile hand-held devices have severe energy constraint. Thus, the innovative, robust and low-power designs of SRAM and level shifter circuits are crucial for modern SoC design. This thesis concentrates on the robust CMOS circuit design of SRAM and level shifter circuits. Specifically, we propose designs for low-power sub-threshold operation. Our 9T-SRAM increases the read and the write noise margin. By employing a new write driver and a single-ended write port, it reduces 50% of the write operation power. In our charge-sharing based 10T-SRAM, bit-line voltages move in opposite direction for every read operation, and it achieves the same amount of differential voltage while consuming lower power. Proposed design dissipates only 25% of the read power by charge-sharing through the read port. Furthermore, it suppresses the BL leakage currents by employing a virtual supply rail. Single-ended write port and write driver are adopted. For interface circuits, we have proposed three different level shifting circuits that convert a sub-threshold input signal into above-threshold levels. Our first design is based on modified Wilson current mirror (MWCMLS), and translates a signal as low as 160 mV into a 1V signal. Focus of the design has been the reduction of energy-delay-product (EDP). Our second design is based on regulated-gate-cascode (NLS). It achieves higher energy-efficiency through feedback mechanism & minimizes the leakage currents by employing transistor stack. Our third design is a two-stage level shifter achieving a very fast operation. Robustness of designs has been verified through extensive Monte-Carlo simulations. Future research directions can be the extension of this work for the complete memory system design, including the power management circuits, large SRAM arrays, and sense amplifiers. Reliability, aging issues, and radiation-hardened designs can be another prospective direction. The development of similar techniques, like charge-sharing and use of level-shifting, for other important circuits and their implementation in newer technologies like PDSOI or FIN/CNT-FET can yet be another future direction.