Design of low dropout regulator with high power supply rejection over wide frequency range

Abstract

Linear regulators are commonly utilized in power management circuits due to their excellent supply noise rejection performance. A novel high-frequency power supply rejection (PSR) low-dropout (LDO) regulator technique is presented in this dissertation. The proposed scheme also targets the low frequency and medium frequency PSR as well as the transient response of the LDO regulator. The proposed LDO regulator utilizes negative capacitance at the gate of the power transistor to enhance the PSR at high frequencies by neutralizing the effect of parasitic capacitances. The loop gain is increased without degrading stability by using multiple high bandwidth gain stages to improve low frequency PSR and load and line regulation. The proposed high PSR LDO regulator is implemented and verified by using a 0.18 ${\upmu}$m CMOS technology. The simulation results show that the LDO regulator is able to achieve a PSR of -58.6 and -67.9 dB at 1 and 10 MHz, respectively.