Full metadata record
DC Field | Value | Language |
---|---|---|
dc.contributor.author | 박재근 | - |
dc.date.accessioned | 2019-12-08T19:53:30Z | - |
dc.date.available | 2019-12-08T19:53:30Z | - |
dc.date.issued | 2018-08 | - |
dc.identifier.citation | APPLIED PHYSICS LETTERS, v. 113, no. 5, Article no. 052103 | en_US |
dc.identifier.issn | 0003-6951 | - |
dc.identifier.issn | 1077-3118 | - |
dc.identifier.uri | https://aip.scitation.org/doi/10.1063/1.5040426 | - |
dc.identifier.uri | https://repository.hanyang.ac.kr/handle/20.500.11754/119780 | - |
dc.description.abstract | We proposed a two-terminal-electrode vertical thyristor and investigated its suitability as a cross point memory cell without a selector from the viewpoints of p(+)- and n(+)-base region width and a vertically stacked doped-epitaxial-Si layer structure such as p(++)-emitter/n(+)-base/p(+)-base/n(++)-emitter or n(++)-emitter/p(+)-base/n(+)-base/p(++)-emitter. The proper p(+)- and n(+)-base-region width (i.e., 160 nm) and p(++)emitter/n(+)-base/p(+)-base/n(++)-emitter layer structure could enable the development of a cross-point memory cell using the half bias concept by preventing misfit dislocations at the junctions between the n(++)-emitter and p(+)-base or n(+)-base and p(++)-emitter. It was also found that generation of the misfit dislocations originating from B or P atom segregation at junctions during doped-Si epitaxial-layer growth enhanced the strain at the junctions. The misfit dislocations at the junctions were produced when the strain at the junctions was greater than similar to 4 x 10(-4). Published by AIP Publishing. | en_US |
dc.description.sponsorship | This research was supported by Brain Korea 21 PLUS Program in 2018, the MOTIE (Ministry of Trade, Industry & Energy 10069063) and KSRC (Korea Semiconductor Research Consortium) support Program for the Development of the Future Semiconductor Device. | en_US |
dc.language.iso | en_US | en_US |
dc.publisher | AMER INST PHYSICS | en_US |
dc.title | Design of two-terminal-electrode vertical thyristor as cross-point memory cell without selector | en_US |
dc.type | Article | en_US |
dc.relation.no | 5 | - |
dc.relation.volume | 113 | - |
dc.identifier.doi | 10.1063/1.5040426 | - |
dc.relation.page | 52103-52103 | - |
dc.relation.journal | APPLIED PHYSICS LETTERS | - |
dc.contributor.googleauthor | Song, Seung-Hyun | - |
dc.contributor.googleauthor | Kim, Min-Won | - |
dc.contributor.googleauthor | Yoo, Sang-Dong | - |
dc.contributor.googleauthor | Shim, Tae-Hun | - |
dc.contributor.googleauthor | Park, Jea-Gun | - |
dc.relation.code | 2018003212 | - |
dc.sector.campus | S | - |
dc.sector.daehak | COLLEGE OF ENGINEERING[S] | - |
dc.sector.department | DEPARTMENT OF ELECTRONIC ENGINEERING | - |
dc.identifier.pid | parkjgl | - |
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