A 12-Gb/s HDMI 2.1 quarter-rate transmitter in 28-nm bulk CMOS process
- Title
- A 12-Gb/s HDMI 2.1 quarter-rate transmitter in 28-nm bulk CMOS process
- Author
- 유창식
- Keywords
- High-definition multimedia interface (HDMI); Transmitter; Quarter-rate; Driver; CMOS
- Issue Date
- 2018-07
- Publisher
- SPRINGER
- Citation
- ANALOG INTEGRATED CIRCUITS AND SIGNAL PROCESSING, v. 96, no. 2, page. 363-370
- Abstract
- A four-lane 12-Gb/s per lane high-definition multimedia interface (HDMI) 2.1 transmitter is developed in 28-nm bulk CMOS process. To relieve the burden of the generation and distribution of clock, quarter-rate architecture is employed where the duty-cycle and phase spacing errors of multi-phase clock are automatically corrected by analog-digital converter based digital logic. The output driver terminated with 3.3-V supply is implemented only with 1.8- and 1.0-V transistors which are protected from over-voltage stress by double-cascoding with adaptive bias generation. The 4-lane HDMI 2.1 transmitter consumes 12.0-mW/lane at 12-Gb/s and occupies 0.12-mm(2) active area.
- URI
- https://link.springer.com/article/10.1007%2Fs10470-018-1232-3https://repository.hanyang.ac.kr/handle/20.500.11754/119357
- ISSN
- 0925-1030; 1573-1979
- DOI
- 10.1007/s10470-018-1232-3
- Appears in Collections:
- COLLEGE OF ENGINEERING[S](공과대학) > ELECTRONIC ENGINEERING(융합전자공학부) > Articles
- Files in This Item:
There are no files associated with this item.
- Export
- RIS (EndNote)
- XLS (Excel)
- XML