Full metadata record
DC Field | Value | Language |
---|---|---|
dc.contributor.author | 김태환 | - |
dc.date.accessioned | 2019-12-07T11:27:14Z | - |
dc.date.available | 2019-12-07T11:27:14Z | - |
dc.date.issued | 2018-03 | - |
dc.identifier.citation | JOURNAL OF NANOSCIENCE AND NANOTECHNOLOGY, v. 18, no. 3, page. 1944-1947 | en_US |
dc.identifier.issn | 1533-4880 | - |
dc.identifier.issn | 1533-4899 | - |
dc.identifier.uri | https://www.ingentaconnect.com/content/asp/jnn/2018/00000018/00000003/art00065 | - |
dc.identifier.uri | https://repository.hanyang.ac.kr/handle/20.500.11754/118045 | - |
dc.description.abstract | Three-dimensional (3D) NAND flash memory devices having a poly-silicon channel with grain boundaries, the cylindrical macaroni channel being outside the inter-oxide filler layer and inside the tunneling oxide layer, were evaluated. The effects of the grain size, grain boundary trap density, and interface trap density at the interfaces between the channel and the oxide layers on the electrical characteristics of 3D NAND flash memory devices were investigated. The electron density of the channel was changed depending on the grain boundary trap density and the position of the grain boundary trap in the channel. The grain boundary traps increased the potential barrier and decreased the electron density of the channel. The threshold voltage increased with increasing grain boundary trap density and interface trap density. | en_US |
dc.description.sponsorship | This research was supported by Basic Science Research Program through the National Research Foundation of Korea (NRF) funded by the Ministry of Education, Science and Technology (2016R1A2A1A05005502). | en_US |
dc.language.iso | en_US | en_US |
dc.publisher | AMER SCIENTIFIC PUBLISHERS | en_US |
dc.subject | 3D NAND Flash Memory | en_US |
dc.subject | Grain Boundary | en_US |
dc.subject | Interface Trap | en_US |
dc.subject | Threshold Voltage | en_US |
dc.title | Effects of the Grain Boundary and Interface Traps on the Electrical Characteristics of 3D NAND Flash Memory Devices | en_US |
dc.type | Article | en_US |
dc.relation.no | 3 | - |
dc.relation.volume | 18 | - |
dc.identifier.doi | 10.1166/jnn.2018.15000 | - |
dc.relation.page | 1944-1947 | - |
dc.relation.journal | JOURNAL OF NANOSCIENCE AND NANOTECHNOLOGY | - |
dc.contributor.googleauthor | Lee, Jun Gyu | - |
dc.contributor.googleauthor | Kim, Tae Whan | - |
dc.relation.code | 2018011853 | - |
dc.sector.campus | S | - |
dc.sector.daehak | COLLEGE OF ENGINEERING[S] | - |
dc.sector.department | DEPARTMENT OF ELECTRONIC ENGINEERING | - |
dc.identifier.pid | twk | - |
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