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UIBF decoding to lower the error floors of high-rate systematic LDPC codes

Title
UIBF decoding to lower the error floors of high-rate systematic LDPC codes
Author
신동준
Keywords
parity check codes; iterative decoding; UIBF decoding; error floors; high-rate systematic LDPC codes; unreliability based information bit flipping; cyclic redundancy check; decoded codeword; sum product decoding; SP decoding; IEEE 802; 16e standard; SP decoding scheme
Issue Date
2017-02
Publisher
INST ENGINEERING TECHNOLOGY-IET
Citation
ELECTRONICS LETTERS, v. 53, no. 4, p. 247-249
Abstract
An unreliability-based information bit flipping (UIBF) decoding using cyclic redundancy check is proposed to lower the error floors of high-rate systematic low-density parity-check (LDPC) codes. Unsuccessfully decoded codeword is redecoded by the UIBF decoding with very low complexity at the end of every iteration of the sum-product (SP) decoding. The proposed scheme is applied to LDPC codes of the IEEE 802.16e standard. Simulation results show that the proposed scheme effectively lowers the error floors of systematic LDPC codes with smaller number of iterations compared with the conventional SP decoding scheme, which leads to the reduced power consumption and increased data throughput.
URI
https://digital-library.theiet.org/content/journals/10.1049/el.2016.2827https://repository.hanyang.ac.kr/handle/20.500.11754/112725
ISSN
0013-5194; 1350-911X
DOI
10.1049/el.2016.2827
Appears in Collections:
COLLEGE OF ENGINEERING[S](공과대학) > ELECTRONIC ENGINEERING(융합전자공학부) > Articles
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