Full metadata record
DC Field | Value | Language |
---|---|---|
dc.contributor.author | 최창환 | - |
dc.date.accessioned | 2019-10-11T01:45:21Z | - |
dc.date.available | 2019-10-11T01:45:21Z | - |
dc.date.issued | 2019-04 | - |
dc.identifier.citation | SOLID-STATE ELECTRONICS, v. 154, Page. 1-6 | en_US |
dc.identifier.issn | 0038-1101 | - |
dc.identifier.issn | 1879-2405 | - |
dc.identifier.uri | https://www.sciencedirect.com/science/article/pii/S0038110118303873?via%3Dihub | - |
dc.identifier.uri | https://repository.hanyang.ac.kr/handle/20.500.11754/110977 | - |
dc.description.abstract | In this study, we have demonstrated 3D fin-structured channel Silicon-On-Insulator (SOI) tunneling field effect transistor (TFET) to enhance transistor on-current (I-on) by reducing leakage current and enhancing gate controllability. By comparing with planar TFET, the subthreshold swing (S.S) value is apparently reduced by similar to 20 mV/dec with increased I-on using fin-typed TFET. Moreover, we have investigated impact of the interfacial layer (IL) modulation on the electrical characteristics of each planar TFET and fin-typed TFET, where IL modulation was performed by adopting modified chemical oxide as well as interface treatment. The IL modulation is substantial on the fin-typed TFET in terms of off leakage current (I-off) as well as threshold voltage instability (Delta V-th) against electrical stress, indicating 3D channel is more sensitive to interface condition. Our results suggest that alternative 3D structure with an appropriate interface treatment might be beneficial to attain better I-on while keeping lower S.S and I-off. | en_US |
dc.description.sponsorship | This work was supported by the Future Semiconductor Device Technology Development Program (10080689) funded by MOTIE (Ministry of Trade, Industry & Energy) and KSRC (Korea Semiconductor Research Consortium) as well as the Industrial Technology Innovation Program (10054882, Development of dry cleaning technology for nanoscale patterns) funded by the Ministry of Trade, Industry and Energy (MOTIE, Republic of Korea). | en_US |
dc.language.iso | en | en_US |
dc.publisher | PERGAMON-ELSEVIER SCIENCE LTD | en_US |
dc.subject | Tunneling field effect transistor (TFET) | en_US |
dc.subject | Fin-typed TFET | en_US |
dc.subject | Interfacial layer (IL) | en_US |
dc.subject | Subthreshold swing (S.S) | en_US |
dc.subject | Interface trap (N-it) | en_US |
dc.title | Tunneling field effect transistors (TFETs) with 3D fin-shaped channel structure and their electrical characteristics | en_US |
dc.type | Article | en_US |
dc.relation.volume | 154 | - |
dc.identifier.doi | 10.1016/j.sse.2019.01.003 | - |
dc.relation.page | 1-6 | - |
dc.relation.journal | SOLID-STATE ELECTRONICS | - |
dc.contributor.googleauthor | Lim, Donghwan | - |
dc.contributor.googleauthor | Han, Hoonhee | - |
dc.contributor.googleauthor | Choi, Changhwan | - |
dc.relation.code | 2019000260 | - |
dc.sector.campus | S | - |
dc.sector.daehak | COLLEGE OF ENGINEERING[S] | - |
dc.sector.department | DIVISION OF MATERIALS SCIENCE AND ENGINEERING | - |
dc.identifier.pid | cchoi | - |
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