Modeling and Analysis for Optimal PVR Implementation

Abstract

This paper presents a new methodology of modeling and analyzing required elementsff to design an HDDTV PVR (High Definition Digital Television Personal Video Recorder) with efficient architecture. The bus modeling method is based on the RMS (Rate Monotonic Scheduling) algorithm and provides a convenient way to predict the performance of real-time PVR systems and to modify its architecture with optimal resources. From the analysis, we could design PVR whose real-time performance is verified. We also developed Time-shifter ASIC chip that is in charge of manipulating HD streams to support various functions like trick-mode play in the PVR.