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dc.contributor.author박성주-
dc.date.accessioned2019-05-20T04:09:53Z-
dc.date.available2019-05-20T04:09:53Z-
dc.date.issued2008-06-
dc.identifier.citationETRI JOURNAL, v. 30, No. 3, Page. 403-411en_US
dc.identifier.issn1225-6463-
dc.identifier.urihttps://onlinelibrary.wiley.com/doi/abs/10.4218/etrij.08.0107.0275-
dc.identifier.urihttp://repository.hanyang.ac.kr/handle/20.500.11754/104696-
dc.description.abstractThis paper introduces an interconnect delay fault test (IDFT) controller on boards and system-on-chips (SoCs) with IEEE 1149.1 and IEEE 1500 wrappers. By capturing the transition signals launched during one system clock, interconnect delay faults operated by different system clocks can be simultaneously tested with our technique. The proposed IDFT technique does not require any modification on boundary scan cells. Instead, a small number of logic gates needs to be plugged around the test access port controller. The IDFT controller is compatible with the IEEE 1149.1 and IEEE 1500 standards. The superiority of our approach is verified by implementation of the controller with benchmark SoCs with IEEE 1500 wrapped cores.en_US
dc.language.isoen_USen_US
dc.publisherELECTRONICS TELECOMMUNICATIONS RESEARCH INSTen_US
dc.subjectdesign for testabilityen_US
dc.subjectsystem-on-chipen_US
dc.subjectIEEE 1149.1en_US
dc.subjectIEEE 1500en_US
dc.subjectmultiple clock domainsen_US
dc.titleInterconnect Delay Fault Test on Boards and SoCs with Multiple Clock Domainsen_US
dc.typeArticleen_US
dc.identifier.doi10.4218/etrij.08.0107.0275-
dc.relation.journalETRI JOURNAL-
dc.contributor.googleauthorYi, Hyunbean-
dc.contributor.googleauthorSong, Jaehoon-
dc.contributor.googleauthorPark, Sungju-
dc.relation.code2008202959-
dc.sector.campusE-
dc.sector.daehakCOLLEGE OF COMPUTING[E]-
dc.sector.departmentDIVISION OF COMPUTER SCIENCE-
dc.identifier.pidpaksj-
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COLLEGE OF COMPUTING[E] > COMPUTER SCIENCE(소프트웨어학부) > Articles
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