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dc.contributor.author김희준-
dc.date.accessioned2019-05-20T02:24:22Z-
dc.date.available2019-05-20T02:24:22Z-
dc.date.issued2008-06-
dc.identifier.citation대한전자공학회 2008년 하계종합학술대회, Page. 1069-1070en_US
dc.identifier.urihttp://www.dbpia.co.kr/Journal/ArticleDetail/NODE01017399-
dc.identifier.urihttps://repository.hanyang.ac.kr/handle/20.500.11754/104645-
dc.description.abstractThis paper presents a high efficient two-stage interleaved synchronous buck CMOS DC-DC converter. The proposed circuit has a fixed duty cycle as 0.5 by an added buck converter. And it causes the best ripple cancelation of the output current ripple. The proposed circuit was simulated by HSPICE with a standard CMOS 0.35㎛ process parameter.en_US
dc.language.isoko_KRen_US
dc.publisher대한전자공학회en_US
dc.title고효율 2단 인터리브 동기정류형 벅 컨버터en_US
dc.title.alternativeA High Efficient, Two-Stage Interleaved Synchronous Buck CMOS DC-DC Converteren_US
dc.typeArticleen_US
dc.contributor.googleauthor박종하-
dc.contributor.googleauthor김훈-
dc.contributor.googleauthor김희준-
dc.sector.campusE-
dc.sector.daehakCOLLEGE OF ENGINEERING SCIENCES[E]-
dc.sector.departmentDIVISION OF ELECTRICAL ENGINEERING-
dc.identifier.pidhjkim-
Appears in Collections:
COLLEGE OF ENGINEERING SCIENCES[E](공학대학) > ELECTRICAL ENGINEERING(전자공학부) > Articles
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