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Soft error study on DDR4 SDRAMs using a 480 MeV proton beam

Title
Soft error study on DDR4 SDRAMs using a 480 MeV proton beam
Author
백상현
Keywords
DDR4 SDRAM; logic upset cluster; retention weak bits; single event upset
Issue Date
2017-04
Publisher
IEEE
Citation
2017 IEEE International Reliability Physics Symposium (IRPS), Page. 1-6
Abstract
This paper is a soft error study on logic upset in control logic, using a 480 MeV proton beam on commercial DDR4 SDRAM components from two different manufacturers. Samples with the same density and speed showed a 1.9x difference in logic cross section depending on the manufacturer. Compared to DDR3 SDRAM, DDR4 SDRAM from the same manufacturer showed about 45% SBU cross-section increase, and 17% logic upset decrease. To understand how the storage capacitance of down-scaling DDR technologies affects soft error, soft error bits were compared to retention weak bits. No evidence was found that indicated that retention weak bits were more sensitive to soft error.
URI
https://ieeexplore.ieee.org/document/7936404https://repository.hanyang.ac.kr/handle/20.500.11754/103252
ISBN
978-1-5090-6641-4
ISSN
1938-1891
DOI
10.1109/IRPS.2017.7936404
Appears in Collections:
COLLEGE OF ENGINEERING SCIENCES[E](공학대학) > ELECTRICAL ENGINEERING(전자공학부) > Articles
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