Full metadata record
DC Field | Value | Language |
---|---|---|
dc.contributor.author | 김학성 | - |
dc.date.accessioned | 2019-03-18T08:11:29Z | - |
dc.date.available | 2019-03-18T08:11:29Z | - |
dc.date.issued | 2016-11 | - |
dc.identifier.citation | IEEE TRANSACTIONS ON COMPONENTS PACKAGING AND MANUFACTURING TECHNOLOGY, v. 6, Issue 11, Page. 1667-1676 | en_US |
dc.identifier.issn | 2156-3950 | - |
dc.identifier.issn | 2156-3985 | - |
dc.identifier.uri | https://ieeexplore.ieee.org/document/7587346 | - |
dc.identifier.uri | https://repository.hanyang.ac.kr/handle/20.500.11754/100952 | - |
dc.description.abstract | In this paper, the warpage simulation of a high-density multilayer printed circuit board (PCB) for solid-state disk drive (SSD) and microelectronic package was performed using the anisotropic viscoelastic shell modeling technique. The thermomechanical properties of various copper patterns were homogenized with the anisotropic shell model, which considered their viscoelastic properties. Then, warpage simulations of an SSD PCB unit/array and a full microelectronic package were performed; these simulations accounted for the initial warpage that occurred during fabrication using ABAQUS combined with a user-defined subroutine. Finally, it was demonstrated that both the maximum warpage and the remaining residual warpage of the full microelectronic package can be accurately predicted. | en_US |
dc.description.sponsorship | This work was supported in part by the Research Fund of Hanyang University under Grant HY-2013, in part by the Semiconductor Industry Collaborative Project between Hanyang University and Samsung Electronics Company, Ltd., in part by the National Research Foundation of Korea Grant funded by the Korean Government (MEST) under Grant 2013M2A2A9043280, and in part by the Industrial Strategic Technology Development Program (In-line Semiconductor Chip/Package Inspection system with THz imaging) funded by the Ministry of Trade, Industry and Energy, Korea, under Grant 10052674. Recommended for publication by Associate Editor I. C. Ume upon evaluation of reviewers' comments. (Corresponding author: Hak-Sung Kim.) | en_US |
dc.language.iso | en | en_US |
dc.publisher | IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC | en_US |
dc.subject | Anisotropic shell model | en_US |
dc.subject | initial warpage | en_US |
dc.subject | microelectronic package | en_US |
dc.subject | printed circuit board (PCB) | en_US |
dc.subject | warpage simulation | en_US |
dc.title | Warpage Simulation of a Multilayer Printed Circuit Board and Microelectronic Package Using the Anisotropic Viscoelastic Shell Modeling Technique That Considers the Initial Warpage | en_US |
dc.type | Article | en_US |
dc.relation.no | 11 | - |
dc.relation.volume | 6 | - |
dc.identifier.doi | 10.1109/TCPMT.2016.2612637 | - |
dc.relation.page | 1667-1676 | - |
dc.relation.journal | IEEE TRANSACTIONS ON COMPONENTS PACKAGING AND MANUFACTURING TECHNOLOGY | - |
dc.contributor.googleauthor | Kim, Do-Hyoung | - |
dc.contributor.googleauthor | Joo, Sung-Jun | - |
dc.contributor.googleauthor | Kwak, Dong-Ok | - |
dc.contributor.googleauthor | Kim, Hak-Sung | - |
dc.relation.code | 2016003029 | - |
dc.sector.campus | S | - |
dc.sector.daehak | COLLEGE OF ENGINEERING[S] | - |
dc.sector.department | DIVISION OF MECHANICAL ENGINEERING | - |
dc.identifier.pid | kima | - |
dc.identifier.orcid | http://orcid.org/0000-0002-6076-6636 | - |
dc.identifier.orcid | http://orcid.org/0000-0003-2675-8912 | - |
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