| 2016-09 | A 65 nm Temporally Hardened Flip-Flop Circuit | 백상현 |
| 2009-10 | A di/dt Compensation Technique in Delay Testing by Disconnecting Power Pins | 백상현 |
| 2011-04 | AC-DC factor sensitivity for DRAM components lifetime under hot-carrier injection | 백상현 |
| 2017-02 | Active Precharge Hammering to Monitor Displacement Damage Using High-Energy Protons in 3x-nm SDRAM | 백상현 |
| 2015-02 | Active-precharge hammering on a row induced failure in DDR3 SDRAMs under 3× nm technology | 백상현 |
| 2017-02 | An alternative approach to measure alpha-particle-induced SEU cross-section for flip-chip packaged SRAM devices: High energy alpha backside irradiation | 백상현 |
| 2014-08 | An Efficient Multiple Cell Upsets Tolerant Content-Addressable Memory | 백상현 |
| 2015-04 | An SEU-Tolerant DICE Latch Design With Feedback Transistors | 백상현 |
| 2009-05 | Analysis of low power sensor node using data compression | 백상현 |
| 2005-03 | Analytical Test Buffer Design For Differential Signaling I/O Buffers by Error Syndrome Analysis | 백상현 |
| 2019-06 | Architectural design tradeoffs in SRAM-based TCAMs | 백상현 |
| 2016-11 | An Area Efficient Stacked Latch Design Tolerant to SEU in 28 nm FDSOI Technology | 백상현 |
| 2016-10 | Assessing alpha-particle-induced SEU sensitivity of flip-chip bonded SRAM using high energy irradiation | 백상현 |
| 2017-07 | BPPT - Bulk potential protection technique for hardened sequentials | 백상현 |
| 2017-07 | BPPT–Bulk Potential Protection Technique for Hardened Sequentials | 백상현 |
| 2005-09 | Built-In Null Detector Design For AC-Coupled Differential Receive Buffer | 백상현 |
| 2012-12 | Characterizing the Capacitive Crosstalk in SRAM Cells Using Negative Bit-Line Voltage Stress | 백상현 |
| 2012-09 | Comparative study of MC-50 and ANITA neutron beams by using 55 nm SRAM | 백상현 |
| 2019-08 | Correctable and uncorrectable errors using large scale DRAM DIMMs in replacement network servers | 백상현 |
| 2023-01 | DDR4 Ball Grid Array Package Intermittent Fracture Effect on Signal Integrity | 백상현 |
