| 2013-06 | Packet-Reduced Ranging Method with Superresolution TOA Estimation Algorithm for Chirp-Based RTLS | 정정화 |
| 2015-11 | Pattern Transformation Method for Digital Camera with Bayer-Like White-RGB Color Filter Array | 정정화 |
| 2011-02 | Performance Optimization of Time Delay Estimation Based on Chirp Spread Spectrum Using ESPRIT | 정정화 |
| 2013-01 | Power bumps and through-silicon-vias placement with optimised power mesh structure for power delivery network in three-dimensional-integrated circuits | 정정화 |
| 2014-09 | Power-aware floorplanning-based power through-silicon-via technology and bump minimisation for three-dimensional power delivery network | 정정화 |
| 2012-02 | Real-Time Digital Image Stabilization for Cell Phone Cameras in Low-Light Environments without Frame Memory | 정정화 |
| 2012-09 | Real-time look-up table-based color correction for still image stabilization of digital cameras without using frame memory | 정정화 |
| 2012-01 | Real-Time LUT-Based Color Correction for Cell Phone Cameras in Low Light Conditions Without Using Frame Memory | 정정화 |
| 2014-08 | Robust self-cancellation-based time-of-arrival estimation algorithm to carrier frequency offset for bi-directional chirp signals | 정정화 |
| 2015-05 | Robust Timing Offset Estimation Using Sub-autocorrelation Functions for Uni- and Bi-directional Chirp Signals | 정정화 |
| 2014-12 | Robust Timing Offset Estimation Using Sub-autocorrelation Functions for Uni- and Bi-directional Chirp Signals | 정정화 |
| 2014-09 | Segmenting a Noisy Low-Depth-of-Field Image Using Adaptive Second-Order Statistics | 정정화 |
| 2011-12 | SNR Enhancement Algorithm Using Multiple Chirp Symbols with Clock Drift for Accurate Ranging | 정정화 |
| 2015-06 | SoC Implementation of Asynchronous Two-Way Ranging System of Chirp pread Spectrum | 정정화 |
| 2012-02 | Subspace-Based Propagation Delay Estimation Robust to Frequency Offset for Two-Way Ranging | 정정화 |
| 2012-03 | A Subspace-Based Two-Way Ranging System Using a Chirp Spread Spectrum Modem, Robust to Frequency Offset | 정정화 |
| 2012-12 | Thermal Aware Buffer Insertion in the Early Stage of Physical Designs | 정정화 |
| 2014-06 | Thermal aware clock tree optimization with balanced clock skew in 3D ICs | 정정화 |
| 2012-05 | Thermal Aware Timing Budget for Buffer Insertion in Early Stage of Physical Design | 정정화 |
| 2014-08 | Thermal-Aware Floorplanning with Min-cut Die Partition for 3D ICs | 정정화 |
