Tunnel Field Effect Transistor with High-K/Metal Gate Stack and Band Gap Engineering

Abstract

With the increasing number of Internet of Things (IoT) technologies implemented in permanent and portable electronic devices, the power dissipation has also increased. The solution for power dissipation can be addressed in two ways: increasing the power supply and reducing the power consumption. Increasing the power supply is not an issue for installation-type appliances or products that are not required to be portable, but it is limited for portable small-sized devices, in which case the power consumption must be reduced. The reduction of power consumption occurs in packaging or wiring processes but, fundamentally, low-power devices are needed to control the amount of power that explosively increases with device integration. Many low-power systems with various structures have been designed and tunnel field-effect transistors (TFETs), which have been studied, are among the promising ones. A TFET has a structure using the bandgap as an energy barrier and a similar behavior as the reversal voltage of diodes when turned on. Subthreshold swings (SS) lower than those of metal-oxide-semiconductor field-effect transistors (MOSFETs) are possible because TFETs are characterized by low off current and not influenced by thermionic emission. The low leakage current and excellent switching performance make them suitable as low-power devices, allowing low drive voltages, especially in complementary metal-oxide semiconductors (CMOSs) operating as inverters. The TFET structure and process are not so different from the MOSFET ones, so the process similarity is more excellent than other low power devices. However, there is the disadvantage of the on current being also low due to a bandgap resistance. The electrical characteristics of TFETs are less effective than the theoretical and simulation information due to the many variables in the junction and gate. The gate dielectric and the metal electrode can be modulated to improve the on current and the SS by enhancing the gate performance itself. And method of improvement can be a general method used in a MOSFET or a new way in a TFET technology. According to many simulation studies, the characteristics of the interface layer can be generally defined based on the interface-trap charge, which should be controlled because it greatly affects TFET characteristics such as the on current and the SS. We investigated how the same phenomenon actually occurs in TFET through various problems in MOSFET and how to improve the interfacial characteristics that have the biggest influence among the abovementioned several variables. To improve the interfacial properties, the thermal treatment with the hydrogen-based gas, which is the most common method for this purpose. In fact, the interface-trap charge was well controlled and the electrical characteristics were improved by this treatment, especially when carried out at high pressure. In addition, we performed atomic layer deposition (ALD), stacking alternately an aluminum and a hafnium oxide film; the ion movement occurred due to imperfect bonding between the atomic layers of metal oxides. The physical thickness of the interfacial layer was reduced, improving the electrical characteristics of the TFET. Although the equivalent oxide thickness and gate leakage current changed according to the composition ratio of the two films, the interface characteristics were improved and the characteristics were improved than those of the general hafnium oxide gate. Moreover, the electrical characteristics of the device were enhanced via the interfacial layer scavenging technique by depositing a small amount of titanium and aluminum layers, which are transition metals, between the gate dielectric and the metal electrode. Experiments were carried out with both direct interfacial layer scavenging, where the transition metal layer was in direct contact with the gate dielectric one, and remote interfacial layer scavenging, where the transition metal layer was separated from the gate dielectric one. Both methods effectively allowed the control of the interface; however, with the direct scavenging approach, the gating ability was improved by stabilizing the interfacial characteristics but the interface was aggressively removed and the device degraded in terms of gate stress immunity. Furthermore, we demonstrated that the influence of the interfacial layer is more critical in case of a is three-dimensional (3D) channel structure of the TFET rather than a planar, hence, the interfacial layer treatment of the 3D channel is more effective for improving its electrical characteristics. For the implementation of a complementary TFET (CTFET), work function modulation was carried out and significant results have been obtained. Titanium nitride was deposited by ALD, the work function was able to finely module the threshold voltage by controlling its physical thickness, and the gate dielectric layer was less damaged than when physical vapor deposited (PVD). There is an acceptor trap moving like a positive charge and a donor trap moving like a negative charge. In TFETs, the acceptor trap is dominant in the N-channels and the donor trap in the P-channels TFET, weakening the electrical properties of the device. The deterioration of the P+/P junctions driven in the N-channels or the degradation of the P/N+ ones in the P-channels could be used to analyze the difference between the acceptor and donor charges; moreover, the amount of each trapped charge can be inferred and analyzed through the changes in the transfer curve. These experiments demonstrated with various analytical methods that the electrical characteristics of Si TFET, such as SS and on current, can be improved by enhancing the interface conditions and also the stress immunity can be enhanced. However, since the on current is determined by the bandgap resistance, its improvement required the use of low bandgap materials and we demonstrated small bandgap TFETs. A bandgap of 0.74–0.88 eV was achieved through the high-quality epitaxial growth of indium gallium arsenide and a vertical channel was formed to fabricate the device. The InGaAs TFET achieved higher on current and improved SS, but exhibited a reduced on/off current ratio compared to the Si TFET. Using a low bandgap material can be considered a decisive factor for obtaining higher on currents. In addition, if the interface stabilization process, the work function control process, and the gate and channel stress immunity analysis can be applied, as done for the Si TFET, better electrical characteristics can be expected. This study could be an important technical basis for enhancing the electrical characteristics by improving the gate characteristics and stress immunity of TFETs, paving the road to their commercialization as promising low-power devices.