Fan-out electronic packaging technology utilizing flip-chip self-alignment
- Fan-out electronic packaging technology utilizing flip-chip self-alignment
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- 플립 칩 자가 정렬 방법 연구를 통한 팬 아웃 전자 패키지 기술
- Hwan Pil PARK
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- Fan-out WLP (FO-WLP) and panel level package (PLP) technologies have received high attention for the high-seed, multifunctional performance of next generation product. However, manufacturing issues such as a die shift and molded warpage during the process have limited the widespread adoption of FO-WLP technology.
The die shift issue can occur when the die-attach machine pick-and-places the die with a certain degree of tolerance and the attached die is then shifted by compressive stress during wafer molding. Subsequent redistribution layer (RDL) process was required for a more accurate position of the die to interconnect the die pad with an RDL via. Therefore, minimizing the die shift value is very important for the advanced device packaging by FO-WLP and FO-PLP technology.
Another major process issues in fan-out package technology is the molded warpage issue before RDL formation process in FO-WLP and panel warpage during build-up the lamination process in FO-PLP. Because excessive warpage may result in trouble during process handling in process such as photolithography, bonding, de-bonding and package sawing and result in the yield loss. The molded wafer or panel warpage was mainly occurred by the coefficient of thermal expansion (CTE) mismatch between molding material and embedded silicon die. Because epoxy molding materials (EMC) for WLP process or resin materials for PLP process have a larger CTE than the silicon dies. Furthermore, warpage issue is more serious in panel level process because panel has a larger processing area than wafer level processing area. Therefore, it is necessary effective solutions to improve the molded warpage by package structure or by optimizing constructed materials properties.
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- GRADUATE SCHOOL[S](대학원) > MATERIALS SCIENCE & ENGINEERING(신소재공학과) > Theses (Ph.D.)
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