A Study of Plasma Dry Cleaning on the Interface Characteristics of Trench Structured MOS Device
- A Study of Plasma Dry Cleaning on the Interface Characteristics of Trench Structured MOS Device
- Myeong Gyoon Chae
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- The scaling-down of the semiconductor devices over the past decades has enabled the implementation of modern advanced devices such as logic fin field effect transistor (FinFET), dynamic random access memory (DRAM), and vertical-NAND (V-NAND) flash. However, in the case of emerging ultra-high aspect ratio and ultra-fine devices, problems of pattern leaning and residual nano-particles in the conventional solution-based wet cleaning process have become critical, and industrial demands and research needs for dry cleaning and hybrid cleaning are exponentially increasing. However, suppression of interface degradation during plasma or chemical reaction as well as the optimization of process parameters are still challenging.
In this study, we investigated the cleaning effect of plasma dry cleaning through the trench structured metal-oxide-semiconductor (MOS) Si device with atomic layer deposited HfO2/TiN gate stack. Compared to non-cleaned devices, dry cleaned devices demonstrate lower stress-induced flatband voltage shift (△VFB), small fresh interface trap density (Dit), and higher restraint of Dit generation (△Dit, ~20x) against high electrical stress. In addition, it was observed that the effect of inhibiting the interface trap formation by increasing the formation activation energy (2.55x). It also means that it is a significant compensation to the critical issue of the Si device, which is the weakest to interface trap generation at midgap energy level. Furthermore, the higher oxide capacitance (Cox) (>33% @1MHz), steeper slope on capacitance-voltage (C-V) curve, more positive flatband voltage (VFB, ~0.7V) and reduced frequency dependency of C-V curve (~52%) were obtained after dry cleaning.
These results stem from its good cleaning effect on residual impurities which deteriorate the electrical performance of MOS device inside the gate dielectric. It is expected that the dry cleaning method will be an alternative knob that minimizes the interface damage while maximizing the cleaning effect in the process based on ultrafine, high aspect ratio Si. Also, these results suggest that in the case of ultra-fine and high aspect ratio device our method can be a more competitive way than conventional wet cleaning.
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- GRADUATE SCHOOL[S](대학원) > MATERIALS SCIENCE & ENGINEERING(신소재공학과) > Theses (Master)
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