76 0

Full metadata record

DC FieldValueLanguage
dc.contributor.author신현철-
dc.date.accessioned2019-02-26T07:57:34Z-
dc.date.available2019-02-26T07:57:34Z-
dc.date.issued2017-09-
dc.identifier.citationIET CIRCUITS DEVICES & SYSTEMS, v. 11, No. 5, Page. 512-519en_US
dc.identifier.issn1751-858X-
dc.identifier.issn1751-8598-
dc.identifier.urihttps://digital-library.theiet.org/content/journals/10.1049/iet-cds.2016.0249-
dc.identifier.urihttps://repository.hanyang.ac.kr/handle/20.500.11754/99241-
dc.description.abstractRegular structures, like datapath, are important components of integrated circuits. Datapath logic is usually placed with high regularity and compactness for higher performance by using manual placement. The authors propose effective datapath regularity extraction and placement (DREP) techniques which simultaneously place datapath logic and random logic. This method detects datapath logic and effectively formats regular datapath structures while optimizing the order of functional stages and placement of datapath blocks. Moreover, the datapath structures are further optimized by using bit-slice order adjustment and partitioning techniques during global placement. Partitioning of a big datapath macro greatly increases the placement flexibility, since partitioned sub-blocks of the datapath macro can be optimally placed with other blocks. A new effective method is also suggested to decide the block to be partitioned and the granularity of partitioning. Similar to the manual placement results, the datapath logic is regularly placed and the datapath cells are aligned well, vertically or horizontally by the DREP techniques. When compared with the state-of-the-art works, the experimental results show that the new techniques produce significantly better results than other methods in terms of half perimeter wire length, Steiner wire length, and routability, measured from the detail routing results.en_US
dc.description.sponsorshipThis work was supported in part by Samsung Electronics Co. We thank Mr. Samuel I. Ward for providing us with the benchmarks and helpful discussions. We also thank the authors of mPL6, NTUplace3, and SimPL for providing their binaries.en_US
dc.language.isoen_USen_US
dc.publisherINST ENGINEERING TECHNOLOGY-IETen_US
dc.subjectmicroprocessor chipsen_US
dc.subjectintegrated circuit designen_US
dc.subjectwires (electric)en_US
dc.subjectnetwork routingen_US
dc.subjectdatapath-intensive circuitsen_US
dc.subjectintegrated circuit componentsen_US
dc.subjectdatapath logicen_US
dc.subjectrandom logicen_US
dc.subjectdatapath regularity extraction and placement techniquesen_US
dc.subjectcircuit designen_US
dc.subjectregular datapath structuresen_US
dc.subjectdatapath block placementen_US
dc.subjectglobal placementen_US
dc.subjectbit-slice order adjustmenten_US
dc.subjectbig datapath macro partitioningen_US
dc.subjectplacement flexibilityen_US
dc.subjectdatapath cellsen_US
dc.subjectDREP techniqueen_US
dc.subjecthalf perimeter wire lengthen_US
dc.subjectSteiner wire lengthen_US
dc.subjectroutabilityen_US
dc.titleEffective regularity extraction and placement techniques for datapath-intensive circuitsen_US
dc.typeArticleen_US
dc.relation.no5-
dc.relation.volume11-
dc.identifier.doi10.1049/iet-cds.2016.0249-
dc.relation.page512-519-
dc.relation.journalIET CIRCUITS DEVICES & SYSTEMS-
dc.contributor.googleauthorWang, Yu-
dc.contributor.googleauthorShin, Hyunchul-
dc.relation.code2017001287-
dc.sector.campusE-
dc.sector.daehakCOLLEGE OF ENGINEERING SCIENCES[E]-
dc.sector.departmentDIVISION OF ELECTRICAL ENGINEERING-
dc.identifier.pidshin-
Appears in Collections:
COLLEGE OF ENGINEERING SCIENCES[E](공학대학) > ELECTRICAL ENGINEERING(전자공학부) > Articles
Files in This Item:
There are no files associated with this item.
Export
RIS (EndNote)
XLS (Excel)
XML


qrcode

Items in DSpace are protected by copyright, with all rights reserved, unless otherwise indicated.

BROWSE