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dc.contributor.advisor권오경-
dc.contributor.authorJeong, Jae-Hoon-
dc.date.accessioned2018-09-18T00:45:47Z-
dc.date.available2018-09-18T00:45:47Z-
dc.date.issued2018-08-
dc.identifier.urihttps://repository.hanyang.ac.kr/handle/20.500.11754/75886-
dc.identifier.urihttp://hanyang.dcollection.net/common/orgView/200000433384en_US
dc.description.abstractRecently, as the mobile and wearable devices are rapidly spreading, the power management integrated circuits (PMICs), which convert a battery voltage to a voltage required for the inner block of the chip, have become more important. These PMICs require a high efficiency for longer battery usage time and a full integration of the chip for smaller device size. To achieve the above requirements, this thesis proposes a fully integrated linear low-dropout (LDO) regulator with less quiescent current to extend the battery usage time. In general, as the quiescent current decreases, the transient response characteristics get worse. Thus, an advanced dynamic biasing (ADB) method is proposed in an attempt to improve the transient response, while reducing the quiescent current. Unlike the conventional dynamic biasing method using a high pass filter, the proposed ADB method detects the load transient without using a high pass filter and determines the bias current according to the load current. Thus, the bias current is maintained low in the steady state, and increased only in the load transient state, thereby greatly reducing the power consumption and achieving fast transient response characteristic. In addition, the chip area can be reduced by eliminating the necessity of the high pass filter, which consists of large resistor and capacitor, and moreover a chip-level full integration can be realized without the output capacitance. The proposed LDO regulator was fabricated in a 0.18-μm CMOS process and occupies a chip area of 0.05 mm2. The transient response characteristics of the output voltage (VOUT) iii according to the variation in the load current was measured. The measurement results show that the settling time, which is a time required to stabilize VOUT, is less than 1.2 μs when the load current varies from heavy load (100 mA) to light load (100 μA). On the other hand, when the load current varies from light to heavy load, the settling time is measured to be less than 0.6 μs. The quiescent current consumed by the LDO regulator is 2 μA at light load. Therefore, the proposed regulator is suitable for mobile applications requiring low power consumption and small form factor.-
dc.publisher한양대학교-
dc.titleFast-Transient Response and Low-Power Capacitor-Less Low-Dropout Regulator-
dc.typeTheses-
dc.contributor.googleauthor정재훈-
dc.contributor.alternativeauthor정재훈-
dc.sector.campusS-
dc.sector.daehak대학원-
dc.sector.department전자컴퓨터통신공학과-
dc.description.degreeMaster-
Appears in Collections:
GRADUATE SCHOOL[S](대학원) > ELECTRONICS AND COMPUTER ENGINEERING(전자컴퓨터통신공학과) > Theses (Master)
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