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COLLEGE OF ENGINEERING[S](공과대학)
ELECTRONIC ENGINEERING(융합전자공학부)
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2018-07
Autonomous high-speed serial link power management depending on required link performance for HMC
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3D-stacked DRAMs
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3D-stacked dynamic RAMs
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active links
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clock synchronisation
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conventional DRAM
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CPU
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high-speed link
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hybrid memory cube
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link performance
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link power consumption reduction
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