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High-Speed Parallel Decimal Multiplication with Redundant Internal Encodings

Title
High-Speed Parallel Decimal Multiplication with Redundant Internal Encodings
Author
Seokbum Ko
Keywords
Decimal arithmetic; parallel multiplication; redundant number system; multioperand SD adder; hybrid prefix network
Issue Date
2013-05
Publisher
IEEE
Citation
IEEE Transactions on Computers, May 2013, 62(5), P.956-968
Abstract
The decimal multiplication is one of the most important decimal arithmetic operations which have a growing demand in the area of commercial, financial, and scientific computing. In this paper, we propose a parallel decimal multiplication algorithm with three components, which are a partial product generation, a partial product reduction, and a final digit-set conversion. First, a redundant number system is applied to recode not only the multiplier, but also multiples of the multiplicand in signed-digit (SD) numbers. Furthermore, we present a multioperand SD addition algorithm to reduce the partial product array. Finally, a digit-set conversion algorithm with a hybrid prefix network to decrease the number of the logic gates on the critical path is discussed. An analysis of the timing delay and an HDL model synthesized under 90 nm technology show that by considering the tradeoff of designs among three components, the overall delay of the proposed 16 x 16-digit multiplier takes about 11 percent less timing delay with 2 percent less area compared to the current fastest design.
URI
http://ieeexplore.ieee.org/abstract/document/6138855/http://hdl.handle.net/20.500.11754/44688
ISSN
0018-9340
DOI
10.1109/TC.2012.35
Appears in Collections:
COLLEGE OF ENGINEERING[S](공과대학) > COMPUTER SCIENCE(컴퓨터소프트웨어학부) > Articles
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