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dc.contributor.author배석주-
dc.date.accessioned2018-02-18T02:43:31Z-
dc.date.available2018-02-18T02:43:31Z-
dc.date.issued2012-06-
dc.identifier.citationInternational journal of production research, Vol.50, No.12 [2012], 3274-3287en_US
dc.identifier.issn0020-7543-
dc.identifier.urihttp://eds.b.ebscohost.com/eds/detail/detail?vid=0&sid=42172bab-a479-43a6-b5e9-af74c8a7129c%40sessionmgr104&bdata=Jmxhbmc9a28mc2l0ZT1lZHMtbGl2ZQ%3d%3d#AN=77058500&db=bth-
dc.identifier.urihttp://hdl.handle.net/20.500.11754/37939-
dc.description.abstractThe integrated circuits (ICs) on wafers are highly vulnerable to defects generated during the semiconductor manufacturing process. The spatial patterns of locally clustered defects are likely to contain information related to the defect generating mechanism. For the purpose of yield management, we propose a multi-step adaptive resonance theory (ART1) algorithm in order to accurately recognise the defect patterns scattered over a wafer. The proposed algorithm consists of a new similarity measure, based on the p-norm ratio and run-length encoding technique and pre-processing procedure: the variable resolution array and zooming strategy. The performance of the algorithm is evaluated based on the statistical models for four types of simulated defect patterns, each of which typically occurs during fabrication of ICs: random patterns by a spatial homogeneous Poisson process, ellipsoid patterns by a multivariate normal, curvilinear patterns by a principal curve, and ring patterns by a spherical shell. Computational testing results show that the proposed algorithm provides high accuracy and robustness in detecting IC defects, regardless of the types of defect patterns residing on the wafer.en_US
dc.description.sponsorshipGyunghyun Choi's work was supported by the research fund of Hanyang University (HY-2000). Chunghun Ha's work was partly supported by the Korea Research Foundation Grant funded by the Korean Government (MOEHRD, Basic Research Promotion Fund) (KRF-2007-331-D00545). Suk Joo Bae's work (2011-0016598) was supported by Mid-career Researcher Program through NRF grant funded by the MEST.en_US
dc.language.isoenen_US
dc.publisherTAYLOR & FRANCIS LTD, 4 PARK SQUARE, MILTON PARK, ABINGDON OX14 4RN, OXON, ENGLANDen_US
dc.subjectspatial defectsen_US
dc.subjectneural networken_US
dc.subjectpattern recognitionen_US
dc.subjectsimilarityen_US
dc.subjectwafer mapen_US
dc.subjectyield managementen_US
dc.titleMulti-step ART1 algorithm for recognition of defect patterns on semiconductor wafersen_US
dc.typeArticleen_US
dc.relation.no12-
dc.relation.volume50-
dc.identifier.doi10.1080/00207543.2011.574502-
dc.relation.page3274-3287-
dc.relation.journalINTERNATIONAL JOURNAL OF PRODUCTION RESEARCH-
dc.contributor.googleauthorChoi, Gyunghyun-
dc.contributor.googleauthorKim, Sung-Hee-
dc.contributor.googleauthorHa, Chunghun-
dc.contributor.googleauthorBae, Suk Joo-
dc.relation.code2012204303-
dc.sector.campusS-
dc.sector.daehakCOLLEGE OF ENGINEERING[S]-
dc.sector.departmentDEPARTMENT OF INDUSTRIAL ENGINEERING-
dc.identifier.pidsjbae-
Appears in Collections:
COLLEGE OF ENGINEERING[S](공과대학) > INDUSTRIAL ENGINEERING(산업공학과) > Articles
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