Research on the 3D NAND flash memory with Ga-based channel materials

Abstract

3D NAND Flash technology is currently being developed and commercialized due to the scaling limitation of conventional planar NAND flash. Over the past few years, several companies have developed vertically stacked NAND cells with high density and low bit cost. Among them, structures such as Bit-Cost Scalable (BiCS), Pipe-shaped Bit Cost Scalable (P-BiCS) and Terabit Cell Array Transistor (TCAT) have been proposed. However, 3D NAND flash memories have additional problems with their electrical characteristics, and most 3D NAND flash memories use poly-Si as channel material instead of consecutive single-crystalline silicon (c-Si). In the poly-Si channel, which has some critical concerns such as large variability caused by the random distribution of grain boundaries, low mobility, and reliability must be resolved. In NAND Flash applications, low mobility is not a crucial issue because the large page size recompenses the slow latency of read operation. Regarding memory cell distribution, the conductive material fabricated using poly-Si channel in 3D NAND flash causes a extensive distribution, and larger Vt variation comes from the impact of grain boundaries and its applicable traps. Due to the program and erase operation algorithm, the dispersion is able to tighten using a successfully designed algorithm [1]. However, poly-Si conduction is dominated by the scattering events and charged defects in grain boundaries, resulting in low current. A feasible solution to increase the drive current (ID) was already studied in : Thermal annealing is used to recover grain boundaries and interface defects and to engineer the poly-Si grain size. On the other hand, Ⅲ-Ⅴ group compounds for higher electron mobility are attractive alternative to Si [2].