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A Study on Properties Improvement of Tin Disulfide by Thermal Atomic Layer Deposition

Title
A Study on Properties Improvement of Tin Disulfide by Thermal Atomic Layer Deposition
Author
Giyul Ham
Advisor(s)
Hyeongtag Jeon
Issue Date
2017-08
Publisher
한양대학교
Degree
Doctor
Abstract
Currently, electronic products tend to favor human-friendly designs that can provide convenience to human beings. This requires transparent electronic device that are lightweight, portable and flexible/wearable. The development of flexible/wearable electronic devices can be applied to a wide range of application such as flexible display, wearable computer, healthcare, robots and energy industrial. During the past few decades, the core electronics are silicon-based transistors. However, silicon has a materials limitation in its mechanical/electrical properties for application to next generation electronic devices. Since graphene has been found to have very good mechanical/electrical/optical properties, research into various applications such as chemistry, materials, and electronics has started to explode explosively. However, graphene does not have a bandgap and exhibits the characteristics of semi-metals other than semiconductors, and has material limitations in the commercialization of transistor devices as channels. In order to solve this problem, a layered structure material similar to graphene began to be noticed. Transition metal dichalcogenides (TMDCs) such as MoS2 and WS2 have been actively studied. They have excellent switching characteristics (Ion/Ioff) as transistor elements because TMDCs have band gaps. However, since a high-temperature process is required to form TMDCs, it has a disadvantage that it can not be formed directly on a flexible substrate. In this thesis, we have studied basic characteristics of tin disulfide (SnS2) similar to TMDCs and studied transistors using it. SnS2 can be formed at a lower temperature than TMDCs and has a band gap of 2.1-2.4 eV. In addition, it has a high charge mobility of 230cm2V-1s-1 and is applicable to high performance transistors. However, the present SnS2 was formed by a mechanical stripping method or a chemical vapor deposition method. Therefore, we have studied SnS2 deposition by atomic layer deposition, which has its advantages. In comparison to its methods, ALD has several advantages, such as a high thin film quality at relatively low temperatures, precise angstrom (Å)-level control of film thicknesses, high uniformity for large areas. SnS2 deposited by atomic layer deposition was able to form below 150 ℃ of process temperature. This process temperature can be deposited directly on the flexible substrate. For application to flexible electronic devices, the thickness of SnS2 should be reduced. Therefore, the characteristics of SnS2 were analyzed according to the thickness. The crystallinity decreased as the thickness of SnS2 decreased. In order to improve the quality of the thin SnS2, it was annealed in a sulfur atmosphere. The annealed SnS2 was confirmed to have a layered structure by improved crystallinity through TEM analysis. In the sulfur atmosphere, the crystallinity of SnS2 was improved by annealing temperature. However, the crystallinity of SnS2 annealed at 350 ℃ was confirmed to be lowered by XRD and RAMAN analysis. It can be concluded that the thickness of annealed SnS2 decreased at 350 ℃. Therefore, an annealing temperature of 300 ℃ is a stable process condition. The bottom-gated transistor with annealed SnS2 showed switching characteristics and n-type characteristics. However, the carrier mobility and Ion/Ioff, which are major performance indicators of the transistor, were not good. In the process of patterning the SnS2 as a channel, SnS2 is damaged by the photo resist (PR) etchant. Further, adhesion between the substrate and SnS2 is poor. Therefore, it was expected that the device performance would be improved if the adhesion to the substrate was improved while SnS2 was not damaged by the etchant. The ZrO2 thin film was used to prevent damage by etchant and to improve the adhesion between SnS2 and substrate. As a result, the carrier mobility and Ion/Ioff were improved about 10 times compared to conventional device without ZrO2 adhesion and passivation layer. We have improved the annealing process to form few-layer SnS2. First, the atmosphere of annealing was modified by using H2S gas, which is more reactive than sulfur powder, and the annealing temperature was increased step-by-step. In the conventional sulfur powder atmosphere, the 350 °C annealed SnS2 was found to be reduced in thickness, but 350 °C step-by-step annealed SnS2 at H2S atmosphere did not decrease in thickness. Also, crystallinity was further improved. Using this annealing process, we could form a few-layer SnS2 with a layered structure. In order to fabricate an optimal few-layer SnS2 transistor in future, it is necessary to study the switching characteristics of few-layer SnS2 by thickness, and a top-gated transistor using a gate dielectric with high dielectric constant is needed.
URI
http://hdl.handle.net/20.500.11754/33424http://hanyang.dcollection.net/common/orgView/200000430876
Appears in Collections:
GRADUATE SCHOOL[S](대학원) > MATERIALS SCIENCE & ENGINEERING(신소재공학과) > Theses (Master)
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