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Variation-Tolerant Sensing Circuit for Spin-Transfer Torque MRAM

Title
Variation-Tolerant Sensing Circuit for Spin-Transfer Torque MRAM
Author
유창식
Keywords
CMOS; magnetic tunneling junction (MTJ); read disturbance; sensing circuit; spin-transfer torque magnetic random access memory (STT-MRAM); variation tolerance
Issue Date
2015-12
Publisher
IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
Citation
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS, v. 62, NO 12, Page. 1134-1138
Abstract
A sensing circuit is described for a spin-transfer torque magnetic random access memory (STT-MRAM). The sensitivity to the variations of magnetic tunneling junction (MTJ) resistance and transistor parameters is reduced by employing the degenerated cross-coupled sensing circuit (DCCSC). The reference cell is also implemented to minimize the variation sensitivity and avoid any read disturbance. The proposed DCCSC and the reference cell are applied to a 64-kb STT-MRAM array. Simulation results with a 65-nm CMOS process parameter show that the sensing margin is larger than 500 mV, for both the parallel and antiparallel states, and the access time is 2 ns, and the energy per bit sensing is only 0.195 pJ, assuming that the variation of the MTJ resistance is +/-20% and tunneling magnetoresistance ratio is 100%.
URI
http://ieeexplore.ieee.org/document/7202854/?arnumber=7202854&tag=1http://hdl.handle.net/20.500.11754/30195
ISSN
1549-7747; 1558-3791
DOI
10.1109/TCSII.2015.2468971
Appears in Collections:
COLLEGE OF ENGINEERING[S](공과대학) > ELECTRONIC ENGINEERING(융합전자공학부) > Articles
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