Area and power efficient decimal carry-free adder

Abstract

As decimal floating-point (DFP) is better than binary floating-point in commercial and financial computing including billing systems, currency conversion, tax calculation and banking, many research activities have been focused on improving the performance of the DFP arithmetic unit recently. To achieve the high performance of the DFP arithmetic unit, a fast decimal fixed-point adder is the most important building block. The conventional three steps carry-free signed digit (SD) addition algorithm is first investigated. A new method for the decimal SD addition and subtraction based on the digit set [-9, 9] is proposed. Additionally, a digit-set converter which can directly generate the absolute value of the result is proposed. A model of the proposed decimal SD adder is implemented in VHDL. After exhaustive tests to ensure the correctness, the proposed design was synthesised in STM 90 nm technology. The results show that the proposed adder has a lower power and area consumption compared with previous designs.