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Conditional termination check min-sum algorithm for efficient LDPC decoders

Title
Conditional termination check min-sum algorithm for efficient LDPC decoders
Author
정기석
Keywords
low-power LDPC decoder; min-sum algorithm
Issue Date
2015-11
Publisher
IEICE-INST ELECTRONICS INFORMATION COMMUNICATIONS ENG
Citation
IEICE ELECTRONICS EXPRESS, v. 12, NO 24, Aritcle Number 20150738 Page. 1-6
Abstract
Conditional termination check min-sum algorithm (MSA) using the difference of the first two minima is proposed for faster decoding speed and lower power consumption of low-density parity-check (LDPC) code decoders. Judging from the size of the difference in LDPC decoding scheduling, the proposed method dynamically decides whether the termination checking steps will be skipped or not. The simulation results show that the decoding speed is improved up to 7%, and the power consumption is reduced by up to 16.43% without any loss of error correcting performance. Also, the additional hardware cost of the proposed method is negligible compared to conventional LDPC decoders.
URI
https://www.jstage.jst.go.jp/article/elex/12/24/12_12.20150738/_articlehttp://hdl.handle.net/20.500.11754/28959
ISSN
1349-2543
DOI
10.1587/elex.12.20150738
Appears in Collections:
COLLEGE OF ENGINEERING[S](공과대학) > ELECTRONIC ENGINEERING(융합전자공학부) > Articles
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