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Optimization of Multi-Channel BCH Error Decoding for Common Case

Title
Optimization of Multi-Channel BCH Error Decoding for Common Case
Author
오현옥
Keywords
Force; Error correction codes; Polynomials; Throughput; Clocks
Issue Date
2015-10
Publisher
ACM/IEEE
Citation
2015 International Conference on Compilers, Architecture and Synthesis for Embedded Systems, CASES 2015 10 November 2015, Article number 7324546, Pages 59-68
Abstract
This paper proposes a new method to optimize a BCH error correction decoder in multi-channel configurations. We break the BCH decoding process into its three basic blocks: syndrome calculation, the error locator polynomial generation, and the roots of the error locator polynomial computation. While an existing multi-channel BCH decoder consists of several single-channel BCH decoders operating in parallel, this paper utilizes a pooled group of shared decoding blocks. By considering the frequency of errors, the proposed pooled group approach requires fewer hardware blocks than in a traditional multi-channel configuration with a negligible impact on performance. Combined with a specialized root finding unit for blocks with only 1 error, our scheme reduces hardware area by 47%-71% and dynamic power by 44%-59% with 2% performance degradation in typical NAND flash systems. With a constant hardware area, the proposed scheme can improve throughput by 3x-5x or NAND flash lifetime by 1.4x-4.5x.
URI
http://ieeexplore.ieee.org/document/7324546/authorshttp://hdl.handle.net/20.500.11754/28282
ISBN
978-1-4673-8320-2
DOI
10.1109/CASES.2015.7324546
Appears in Collections:
COLLEGE OF ENGINEERING[S](공과대학) > INFORMATION SYSTEMS(정보시스템학과) > Articles
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