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Fermi-Level Unpinning Using a Ge-Passivated Metal-Interlayer-Semiconductor Structure for Non-Alloyed Ohmic Contact of High-Electron-Mobility Transistors

Title
Fermi-Level Unpinning Using a Ge-Passivated Metal-Interlayer-Semiconductor Structure for Non-Alloyed Ohmic Contact of High-Electron-Mobility Transistors
Author
최창환
Keywords
Fermi level unpinning; gallium arsenide; germanium; specific contact resistivity; passivation
Issue Date
2015-09
Publisher
IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
Citation
IEEE ELECTRON DEVICE LETTERS, v. 36, NO 9, Page. 884-886
Abstract
We demonstrate the use of germanium passivation in conjunction with a ZnO interlayer in a metal-interlayer-semiconductor structure in a source/drain (S/D) contact. The Fermi-level pinning problem resulting in the large contact resistances in S/D contacts is effectively alleviated by inserting a thin Ge passivation layer and a ZnO interlayer, passivating the GaAs surface and reducing the metal-induced gap states on the GaAs surface, respectively. The specific contact resistivity for the Ti/ZnO/Ge/n-GaAs (similar to 2 x 10(18) cm(-3)) structure exhibits a similar to 1660x reduction compared with that of a Ti/n-GaAs structure. These results suggest that the proposed structure shows promise as a nonalloyed ohmic contact in high-electron-mobility transistors.
URI
http://ieeexplore.ieee.org/abstract/document/7151781/http://hdl.handle.net/20.500.11754/27343
ISSN
0741-3106; 1558-0563
DOI
10.1109/LED.2015.2453479
Appears in Collections:
COLLEGE OF ENGINEERING[S](공과대학) > MATERIALS SCIENCE AND ENGINEERING(신소재공학부) > Articles
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