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Optimal Checkpoint Selection with Dual-Modular Redundancy Hardening

Title
Optimal Checkpoint Selection with Dual-Modular Redundancy Hardening
Author
오현옥
Keywords
Checkpoint; task graph; multiprocessor; reliability; optimal algorithm
Issue Date
2015-07
Publisher
IEEE COMPUTER SOC
Citation
IEEE TRANSACTIONS ON COMPUTERS, v. 64, NO 7, Page. 2036-2048
Abstract
With the continuous scaling of semiconductor technology, failure rate is increasing significantly so that reliability becomes an important issue in multiprocessor system-on-chip (MPSoC) design. We propose an optimal checkpoint selection with task duplication hardening to tolerate transient faults. A target application is specified in a task graph, and the schedule/checkpoint placements are determined at design time. The proposed optimal algorithm minimizes the checkpoint overhead with a latency constraint. Experimental results show that the proposed algorithm effectively reduces the minimum end-to-end latency to perform a fault-tolerant schedule. In addition, the proposed algorithm dramatically decreases the checkpointing overhead on uniprocessor and multiprocessor systems compared with a greedy approach and an equidistant algorithm.
URI
http://ieeexplore.ieee.org/abstract/document/6880324/http://hdl.handle.net/20.500.11754/26588
ISSN
0018-9340; 1557-9956
DOI
10.1109/TC.2014.2349492
Appears in Collections:
COLLEGE OF ENGINEERING[S](공과대학) > INFORMATION SYSTEMS(정보시스템학과) > Articles
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