Full metadata record
DC Field | Value | Language |
---|---|---|
dc.contributor.author | Seokbum Ko | - |
dc.date.accessioned | 2017-02-22T04:31:25Z | - |
dc.date.available | 2017-02-22T04:31:25Z | - |
dc.date.issued | 2015-06 | - |
dc.identifier.citation | ELECTRONICS LETTERS, v. 51, NO 12, Page. 895-897 | en_US |
dc.identifier.issn | 0013-5194 | - |
dc.identifier.issn | 1350-911X | - |
dc.identifier.uri | http://ieeexplore.ieee.org/document/7122465/?arnumber=7122465 | - |
dc.identifier.uri | http://hdl.handle.net/20.500.11754/25614 | - |
dc.description.abstract | Hardware implementation of the fast Fourier transform (FFT) function consists of multiple consecutive arithmetic operations over complex numbers. Applying floating-point arithmetic to FFT coprocessors leads to a wider dynamic range and allows the coprocessor to collaborate with general purpose processors via the standard floating-point arithmetic. This offloads compute-intensive tasks from the primary processor and overcomes floating-point concerns such as scaling and overflow/underflow detection. The downside, however, is that floating-point units are slower than the fixed-point counterparts. One of the popular ways to improve the speed of floating-point FFT units is to merge the arithmetic operations inside the butterfly units of a FFT architecture. This leads to a butterfly architecture based on multioperand adders. Butterfly units are designed, in two of the most recent works, using three-operand and four-operand adders. However, the work reported here by the present authors goes further and a butterfly architecture based on a five-operand adder is proposed. Simulation results demonstrate that the proposed butterfly architecture is 50% smaller than the fastest previous work with about 17% latency overhead. Compared with the smallest previous work, the proposed design is 47% smaller and 8% faster. | en_US |
dc.description.sponsorship | This work was supported by the Natural Sciences and Engineering Research Council of Canada (NSERC). | en_US |
dc.language.iso | en | en_US |
dc.publisher | INST ENGINEERING TECHNOLOGY-IET | en_US |
dc.subject | number theory | en_US |
dc.subject | adders | en_US |
dc.subject | coprocessors | en_US |
dc.subject | fast Fourier transforms | en_US |
dc.subject | floating point arithmetic | en_US |
dc.title | Area efficient floating-point FFT butterfly architectures based on multi-operand adders | en_US |
dc.type | Article | en_US |
dc.relation.no | 12 | - |
dc.relation.volume | 51 | - |
dc.identifier.doi | 10.1049/el.2015.0342 | - |
dc.relation.page | 895-895 | - |
dc.relation.journal | ELECTRONICS LETTERS | - |
dc.contributor.googleauthor | Kaivani, Amir | - |
dc.contributor.googleauthor | Ko, Seok-Bum | - |
dc.relation.code | 2015001404 | - |
dc.sector.campus | S | - |
dc.sector.daehak | COLLEGE OF ENGINEERING[S] | - |
dc.sector.department | DEPARTMENT OF COMPUTER SCIENCE | - |
dc.identifier.pid | kosby | - |
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