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Parallelizing SHA-1 (vol 12, 20150371, 2015)

Title
Parallelizing SHA-1 (vol 12, 20150371, 2015)
Author
원유집
Keywords
Cryptography; Field-Programmable Gate Array (FPGA); Hardware Imple; Hash Functions; Secure Hash Algorithm (SHA)
Issue Date
2015-06
Publisher
IEICE-INST ELECTRONICS INFORMATION COMMUNICATIONS ENG
Citation
IEICE ELECTRONICS EXPRESS, v. 12, NO 14, Page. 1-12
Abstract
In this paper, we propose the parallel architecture for high speed calculations of SHA-1, a widely used cryptographic hash function. Parallel SHA-1 consists of a number of base modules which process the message digest in parallel manner. The base module uses state of art SHA-1 acceleration techniques: loop unfolding, pre-processing, and pipelining. We achieved the performance improvement of 5.8% over the pipeline architecture that is known to have nearly achieved the theoretical performance limit. We implemented our system on the Xilinx Virtex-6 FPGA and verified the operations by interfacing it with MicroBlaze soft processor core.
URI
https://www.jstage.jst.go.jp/article/elex/advpub/0/advpub_12.20150371/_articlehttp://hdl.handle.net/20.500.11754/25411
ISSN
1349-2543
DOI
10.1587/elex.12.20150371
Appears in Collections:
COLLEGE OF ENGINEERING[S](공과대학) > COMPUTER SCIENCE AND ENGINEERING(컴퓨터공학부) > Articles
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