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dc.contributor.author원유집-
dc.date.accessioned2016-09-23T01:22:13Z-
dc.date.available2016-09-23T01:22:13Z-
dc.date.issued2015-03-
dc.identifier.citationACM TRANSACTIONS ON STORAGE, v. 11, NO 2, Page. 1-24en_US
dc.identifier.issn1553-3077-
dc.identifier.issn1553-3093-
dc.identifier.urihttp://dl.acm.org/citation.cfm?id=2644818-
dc.identifier.urihttp://hdl.handle.net/20.500.11754/23299-
dc.description.abstractIn this work, we studied the energy consumption characteristics of various SSD design parameters. We developed an accurate energy consumption model for SSDs that computes aggregate, as well as component-specific, energy consumption of SSDs in sub-msec time scale. In our study, we used five different FTLs (page mapping, DFTL, block mapping, and two different hybrid mappings) and four different channel configurations (two, four, eight, and 16 channels) under seven different workloads (from large-scale enterprise systems to small-scale desktop applications) in a combinatorial manner. For each combination of the aforementioned parameters, we examined the energy consumption for individual hardware components of an SSD (micro-controller, DRAM, NAND flash, and host interface). The following are some of our findings. First, DFTL is the most energy-efficient address-mapping scheme among the five FTLs we tested due to its good write amplification and small DRAM footprint. Second, a significant fraction of energy is being consumed by idle flash chips waiting for the completion of NAND operations in the other channels. FTL should be designed to fully exploit the internal parallelism so that energy consumption by idle chips is minimized. Third, as a means to increase the internal parallelism, increasing way parallelism (the number of flash chips in a channel) is more effective than increasing channel parallelism in terms of peak energy consumption, performance, and hardware complexity. Fourth, in designing high-performance and energy-efficient SSDs, channel switching delay, way switching delay, and page write latency need to be incorporated in an integrated manner to determine the optimal configuration of internal parallelism.en_US
dc.description.sponsorshipThis work is sponsored by IT R&D program MKE/KEIT [No. 10035202, Large Scale hyper-MLC SSD Technology Development] and by the MSIP (Ministry of Science, ICT & Future Planning), Korea, under the ITRC (Information Technology Research Center) support program (NIPA-2014-H0301-14-1017) supervised by the NIPA (National IT Industry Promotion Agency).en_US
dc.language.isoenen_US
dc.publisherASSOC COMPUTING MACHINERYen_US
dc.subjectDesignen_US
dc.subjectMeasurementen_US
dc.subjectSSDen_US
dc.subjectNAND flashen_US
dc.subjectenergy consumptionen_US
dc.subjectFTLen_US
dc.subjectparallelismen_US
dc.subjectsimulatoren_US
dc.titleDesign Tradeoffs of SSDs: From Energy Consumption's Perspectiveen_US
dc.typeArticleen_US
dc.relation.no2-
dc.relation.volume11-
dc.identifier.doi10.1145/2644818-
dc.relation.page1-24-
dc.relation.journalACM TRANSACTIONS ON STORAGE-
dc.contributor.googleauthorCho, SeokHei-
dc.contributor.googleauthorPark, Changhyun-
dc.contributor.googleauthorWon, Youjip-
dc.contributor.googleauthorKang, Sooyoung-
dc.contributor.googleauthorCha, Jaehyuk-
dc.contributor.googleauthorYoon, Sungroh-
dc.contributor.googleauthorChoi, Jongmoo-
dc.relation.code2015006139-
dc.sector.campusS-
dc.sector.daehakCOLLEGE OF ENGINEERING[S]-
dc.sector.departmentDEPARTMENT OF COMPUTER SCIENCE-
dc.identifier.pidyjwon-
Appears in Collections:
COLLEGE OF ENGINEERING[S](공과대학) > COMPUTER SCIENCE AND ENGINEERING(컴퓨터공학부) > Articles
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