High-speed two-step single-slope ADC using multi-sampling with partial conversion

Abstract

A multi-sampling method with partial conversion for a low-noise and high-speed analogue-to-digital converter (ADC) is proposed. The proposed multi-sampling method divides the total bits of an ADC into upper and lower bits, and only repeats the lower bit conversion using the two-step ADC architecture. This partial conversion decreases the A/D conversion time, along with noise reduction by multi-sampling. The proposed method with pseudo-multi-sampling or correlated multi-sampling for lower bit conversion reduces the number of clock cycles by 99.7 or 98.8%, respectively, compared with the conventional multi-sampling method.