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Study on Impact of Plasma-Enhanced-Atomic- Layer-Deposition derived High-k Dielectrics on Performance and Reliability of Oxide Thin-Film Transistors

Title
Study on Impact of Plasma-Enhanced-Atomic- Layer-Deposition derived High-k Dielectrics on Performance and Reliability of Oxide Thin-Film Transistors
Other Titles
플라즈마 증진 원자층 증착 기반 고유전 절연막이 산화물 반도체 박막 트랜지스터의 성능과 신뢰성에 미치는 영향에 관한 연구
Author
최철희
Alternative Author(s)
Cheol Hee Choi
Advisor(s)
정재경
Issue Date
2024. 2
Publisher
한양대학교 대학원
Degree
Doctor
Abstract
As conventional silicon-based Field-Effect Transistors (FETs) encounter performance / physical limits, prompting significant interest in new semiconductor materials such as 2D materials and oxide semiconductor (OS) as alternative semiconductor materials to meet the Power / Performance / Area / Cost (PPAC) requirements of FETs. In particular, OS is considered as the most promising semiconductor to replace silicon due to their outstanding characteristics, including high mobility, low leakage current, low process temperature, and uniform deposition properties. Owing to these notable features of OS, a-IGZO semiconductor have been applied in the backplane of active-matrix organic light-emitting diode (AMOLED) displays, serving as the core material for display thin-film transistors (TFTs) to date. Furthermore, the technological advancements in low-temperature polycrystalline silicon and oxide (LTPO), which integrates OS with low-temperature polycrystalline silicon (LTPS), have maximized the efficiency of display driving and secured the potential for innovative form factors. Currently, research focusing on the application of advanced semiconductor transistors extends beyond the display industry. However, due to the limitations of integration in planar structures according to Moore’s Law, there is a simultaneous degradation in transistor performance, such as the occurrence of short channel effects (SCEs). To improve this, scaling down the thickness of the insulating layer to reduce the natural length of the channel becomes a crucial necessity. The scaling of the insulating layer thickness using conventional SiO2 leads to electron tunneling issues during transistor operation, resulting in high leakage current. To overcome this, reducing the equivalent oxide thickness (EOT) by introducing high-k dielectrics is essential, while maintaining the physical thickness of the insulating layer. The reduced EOT can decrease the natural length of the channel, thereby mitigating SCEs and overcoming the integration issues of the transistor. To overcome the integration limits of planar structure transistors, research is underway to apply back-end-of-line (BEOL) transistors in monolithic-3-D (M3D) architecture using advanced semiconductor technology. However, the conventional methods of thin-films deposition through physical vapor deposition (PVD) and chemical vapor eeposition (CVD) encounter limitations in the application of 3D structures due to poor step-coverage and imprecise thickness controllability. To address this challenge, the implementation of atomic layer deposition (ALD) techniques with excellent step-coverage and precise film thickness control becomes essential. This thesis proposes the issues arising from the application of plasma-enhanced atomic layer deposition (PEALD) based high-κ on OS TFTs, presenting potential problems and their solutions. The presence of numerous defects in the high-κ dielectric layer can be controlled through PEALD processes and subsequent treatments, thereby improving the electrical characteristics and reliability of OS TFTs. Furthermore, the degradation of TFTs electrical properties due to the high polarity within the high-κ dielectric layer was investigated by understanding the structural changes in TFTs, and the underlying issues were elucidated through a physical mechanism. Excellent electrical properties for OS TFTs incorporating high- κ dielectric have been achieved through these efforts, and strategies for the application of next- generation TFTs technology have been proposed. In the first chapter, high-performance a-IGTO TFTs were fabricated based on low- temperature processes (≤ 150 ℃) for the development of display backplanes on flexible substrates such as PEN, PET, or PDMS. The introduction of an alumina (Al2O3) insulator using plasma-enhanced atomic layer deposition (PEALD) was explored for top-gate structure TFTs fabrication. During the Al2O3 on IGTO film, the focus was on the effect ofregulating the partial oxygen pressure (PO2) on the extent of defects within the insulator and their impact on TFT characteristics. The a-IGTO TFT with Al2O3 insulator deposited under the PO2 of 2.5% using PEALD was observed a high carrier concentration, which was stem from high intensity of hydrogen concentration within the a-IGTO/Al2O3 film. This led to the diffusion of hydrogen acting as donor-like defects in the a-IGTO channel layer, confirming the semiconductor characteristics of the TFT. Conversely, when incorporating Al2O3 with a PO2 > 10%, excess oxygen acting as acceptor-like defects resulted in a decreased electron concentration in the channel, consequently deteriorating the TFT's mobility, VTH, and reliability. The condition with PO2: 5% exhibited the most stable and superior TFT characteristics. Through this, the influence of oxygen radical density regulated by PO2 during the upper-layer deposition using PEALD processes significantly have an impact on the semiconductor and insulating layers. Ultimately, it markedly contributes to the electrical characteristics of the TFT. In the second part, top-gate structured TFTs based on a-IGZO/HfO2 using PEALD was fabricated and focused on the influence of HfO2 defects on the reliability mechanisms of the TFTs under different annealing atmospheres (ambient, oxygen). The HfO2 deposited via PEALD has a low formation energy for numerous defects, such as oxygen vacancy (VO) or excess oxygen (Oi), within the film, adversely impacting the electrical characteristics like reliability and mobility during TFTs operation. For devices annealed in ambient conditions, an abundance of positive charged defects (VO, interstitial hydrogen (Hi)) within the HfO2 caused an abnormal shift in VTH under PBS reliability. This occurred as the positive charged defects induced electron accumulation at the interface, leading to increase electron density. Simultaneously, excess hydrogen diffused into the semiconductor layer affect on increasing of electron concentration. Conversely, in devices annealed in oxygen, the reduced concentration of VO within HfO2 led to a decrease in positive charged defects. However, the presence of electron-friendly excess oxygen caused a severe shift of VTH under PBS reliability. To address this, the introduction of a 0.7-nm-thick SiO2 interfacial layer was implemented, resulting in improved electrical characteristics and reliability of the TFTs. In the last part, double-gate (DG) structured IGO TFTs with a hafnium oxide (HfO2) high-κ dielectric layer were fabricated. The focal point was the mechanism of HfO2 polarity and its impact on single-gate (SG) and DG operation. The high-κ dielectric layer possesses high polarity within the film, causing phonon and Coulomb scattering during TFT operation, thereby deteriorating TFT performance. To improve this issue, the structure and operation mode of the IGO TFTs were altered. Notably, in DG operation, the dominant electron pathway shifted from the interface to the bulk region, reducing the effects of remote Coulomb scattering (RCS) induced by HfO2 compared to SG operation. Additionally, the introduction of a 5-nm-thick SiO2 interfacial layer minimized interfacial scattering effects. Consequently, a two-fold increase in mobility and a decrease in subthreshold swing (SS) were observed in DG mode, compared SG mode. Furthermore, through DG operation, the stability characteristics of IGO TFTs, which inherently suffers from NBTI reliability degradation due to numerous oxygen defects, were improved inducing rapid recombination of electrons. This resulted in the enhancement of oxide semiconductor characteristics, effectively addressing the deteriorating NBTI reliability.
URI
http://hanyang.dcollection.net/common/orgView/200000725542https://repository.hanyang.ac.kr/handle/20.500.11754/188778
Appears in Collections:
GRADUATE SCHOOL[S](대학원) > DEPARTMENT OF ELECTRONIC ENGINEERING(융합전자공학과) > Theses (Ph.D.)
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