Design of Low Parasitic Inductance Switching Power Cell with Four-Parallel Bare Die Packaged SiC Power Semiconductor using Chip on Board Technique

Abstract

With the increasing demands of high-efficiency power converters. The optimization of power converters switching modules is one of the main concerns, in which enhancing voltage-current characteristics of SiC MOSFET switching configuration plays a significant role in improving efficiency of the power module. The conventional MOSFET TO247 package generates relatively higher parasitic inductance due to internal traces and external gate loop design according to the larger package, which increases the switching time and the overall power loss. In order to reduce the loss, the proposed module considered four parallel connected Bare Die MOSFETs directly attached to the printed-circuit board, creating a sandwich structured power cell half bridge configuration. From parasitic inductance extraction in Ansys Q3D, it was found that the parasitic inductance in turn-on and turn-off loop of each switch decreased by 40% maximum, compared to TO247 switches. By doing Double Pulse Test in LTspice, it is proved that the power loss showed little difference with or without adding parasitic inductance elements. Using Icepak thermal analysis, the heat sink was proposed for the desired structure in acceptable temperature range.