A 0.03 mm(2) delta-sigma modulator with cascaded-inverter amplifier
- Title
- A 0.03 mm(2) delta-sigma modulator with cascaded-inverter amplifier
- Author
- 노정진
- Keywords
- Delta-sigma modulator; Analog-to-digital convertor; Switched-capacitor circuit; OTA
- Issue Date
- 2014-11
- Publisher
- SPRINGER
- Citation
- ANALOG INTEGRATED CIRCUITS AND SIGNAL PROCESSING, v. 81, NO. 2, Page. 495-501
- Abstract
- A single stage inverter is introduced as a replacement for the conventional OTA to implement an inverter-based delta-sigma modulator. It achieves a high power and area efficiency. However, the low DC-gain and gain-bandwidth (GBW) have limited the application. This paper proposes a cascaded-inverter to increase the DC-gain and GBW, while maintaining the advantages of power and area efficiency. By cascading three inverters, the DC-gain is increased from 44 dB to 82 dB, and the GBW is increased from 100 MHz to 697 MHz. A third-order delta-sigma modulator using the proposed cascaded-inverter has been fabricated in a 0.11-mu m CMOS process. When operating from a 1.2-V supply and clocked at 80 MHz, the prototype modulator achieves 59.4-dB peak SNDR over 500-kHz signal bandwidth while consuming 249 mu W. Measurement results demonstrate that the application of the inverter-based amplifier, which is becoming popular due to its high power efficiency, can be extended to significantly higher speed circuits.
- URI
- https://link.springer.com/article/10.1007/s10470-014-0408-8https://repository.hanyang.ac.kr/handle/20.500.11754/183452
- ISSN
- 0925-1030;1573-1979
- DOI
- 10.1007/s10470-014-0408-8
- Appears in Collections:
- COLLEGE OF ENGINEERING SCIENCES[E](공학대학) > ELECTRICAL ENGINEERING(전자공학부) > Articles
- Files in This Item:
There are no files associated with this item.
- Export
- RIS (EndNote)
- XLS (Excel)
- XML