A 20-MHz bandwidth, 75-dB dynamic range, continuous-time delta-sigma modulator with reduced nonidealities
- Title
- A 20-MHz bandwidth, 75-dB dynamic range, continuous-time delta-sigma modulator with reduced nonidealities
- Author
- 노정진
- Keywords
- clock jitter; continuous-time delta-sigma modulator (CT-DSM); current-steering DAC; excess loop delay (ELD); mismatch; nonreturn-to-zero (NRZ); return-to-zero (RZ)
- Issue Date
- 2019-08
- Publisher
- WILEY
- Citation
- INTERNATIONAL JOURNAL OF CIRCUIT THEORY AND APPLICATIONS, v. 47, NO. 8, Page. 1370-1380
- Abstract
- This letter presents a 4-bit continuous-time delta-sigma modulator (CT-DSM) fabricated using a 65-nm CMOS process. The circuit is designed for wide-bandwidth applications, such as those related to wireless communications. This CT-DSM has an oversampling ratio of 16 with a 640-MHz sampling frequency. To reduce the clock jitter sensitivity and excess loop delay effect, the first DAC pulse is a nonreturn-to-zero (NRZ)-type pulse, whereas the second DAC pulse is a return-to-zero (RZ)-type pulse; this is accomplished using a current-steering DAC. In order to reduce mismatch without using a data-weighted averaging circuit, the size and layout of the unit current source in the current-steering DAC are considered carefully. The CT-DSM achieves a signal-to-noise ratio (SNR) of 67.3 dB, a signal-to-noise and distortion ratio (SNDR) of 63.4 dB, and a dynamic range of 75 dB for a 20-MHz signal bandwidth.
- URI
- https://onlinelibrary.wiley.com/doi/10.1002/cta.2665https://repository.hanyang.ac.kr/handle/20.500.11754/183445
- ISSN
- 0098-9886;1097-007X
- DOI
- 10.1002/cta.2665
- Appears in Collections:
- COLLEGE OF ENGINEERING SCIENCES[E](공학대학) > ELECTRICAL ENGINEERING(전자공학부) > Articles
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