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A Study on Millimeter–Wave Reconfigurable Low Noise Amplifier using GaAs pHEMT Process

Title
A Study on Millimeter–Wave Reconfigurable Low Noise Amplifier using GaAs pHEMT Process
Author
고병훈
Alternative Author(s)
Byung Hun Ko
Advisor(s)
김정현
Issue Date
2023. 2
Publisher
한양대학교
Degree
Master
Abstract
본 논문은 0.15–μm GaAs pHEMT process를 이용하여 millimeter–wave (mm–Wave) 대역에서 reconfigurable operation을 위한 Low Noise Amplifier (LNA)를 제안한다. 제안된 구조는 총 4 stage로 구성되어 있고 첫번째와 두번째 drive stage는 39–48 GHz의 10 dB 이상의 광대역gain 특성과 low noise figure (NF) 특성을 확보하기 위해 2 stage common source를 cascade구조로 설계되었다. 세번째 reconfigurable stage 는 common gate로 구성되어 gate bias의 “on/off” operation을 통해 각각 39 GHz, 48 GHz 에서 selectable하게 동작하도록 설계되었다. 또한 세번째와 마지막 stage 사이에 coupled line based diplexing structure를 사용하여 39 GHz, 48 GHz 대역을 선택적으로 동작할 수 있도록 설계되었다. 마지막 네번째 stage는 linearity 를 개선하고 P1dB 확보를 위하여 최적화된 transistor size 의 common source structure로 설계되었다. 제안된 회로는 Low Frequency (LF) mode 일 경우 39 GHz 의 small signal gain 24.8 dB, High Frequency (HF) mode 일 경우 48 GHz의 small signal gain 19.2 dB이다. Noise figure 성능은 HF mode 일 경우 48 GHz에서 5.0 dB, LF mode 일 경우 39 GHz 에서 4.0 dB가 되도록 설계되었다. OP1dB 성능과 DC power consumption은 HF mode 일 경우 48 GHz에서 6.9 dBm, 61.4 mW, LF mode 일 경우 39 GHz 에서 6.8 dBm, 64.7 mW 으로 설계하였다.|This paper proposes a Low Noise Amplifier (LNA) for reconfigurable operation in the millimeter–wave (mm–Wave) band using a 0.15–μm GaAs pHEMT process. The proposed structure consists of a total of 4 stages, and the 1st and 2nd drive stages are designed in a cascade structure with a 2 stage common source to secure a broadband gain of 10 dB or more and low noise figure (NF) characteristics of 39–48 GHz. The 3rd reconfigurable stage consists of a common gate and is designed to operate selectively at 39 GHz and 48 GHz, respectively, through the “on/off” operation of the gate bias. Also, it is designed to selectively operate 39 GHz and 48 GHz bands by using a coupled line based diplexing structure between 3rd and last stage. The last stage which is equal to 4th stage was designed as a common source structure with an optimized transistor size to improve linearity and secure P1dB. The proposed circuit has a small signal gain of 19.2 dB at 48 GHz in High Frequency (HF) mode and 24.8 dB at 39 GHz in Low Frequency (LF) mode. Noise figure performance was designed to be 5.0 dB at 48 GHz in HF mode and 4.0 dB at 39 GHz in LF mode. OP1dB performance and DC power consumption were designed to be 6.9 dBm, 61.4 mW at 48 GHz in HF mode and 6.8 dBm, 64.7 mW at 39 GHz in LF mode.
URI
http://hanyang.dcollection.net/common/orgView/200000654775https://repository.hanyang.ac.kr/handle/20.500.11754/179899
Appears in Collections:
GRADUATE SCHOOL[S](대학원) > DEPARTMENT OF ELECTRICAL AND ELECTRONIC ENGINEERING(전자공학과) > Theses (Master)
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