Tunable 보정 회로를 갖는 Split-CDAC SAR 아날로그-디지털 변환기

Abstract

Capacitor mismatch caused by imperfect manufacturing process is ａ serious issue in split capacitor digital-to-analog converter (DAC) circuit block of successive approximation-register analog-to-digital converters, thereby can degrad the linearity performance. This research proposes foreground calibration techniques to calibrate the capacitor mismatch of Split-capacitor DAC by optimally tuning the capacitance of variable capacitor employed in the DAC. The behavioral simulation results verify enhancement of the integral nonlinearity and the differential nonlinearity.