Process-Portable and Programmable Layout Generation of Digital Circuits in Advanced DRAM Technologies
- Title
- Process-Portable and Programmable Layout Generation of Digital Circuits in Advanced DRAM Technologies
- Author
- 한재덕
- Keywords
- DRAM; Standard cells; Layout; Design automation; Templates
- Issue Date
- 2021-02
- Publisher
- ACM
- Citation
- Design, Automation and Test in Europe Conference and Exhibition (DATE), page. 721-722
- Abstract
- This paper introduces a physical layout design methodology that produces DRC-clean, area-efficient, and programmable layouts of digital circuits in advanced DRAM processes. The proposed methodology automates the layout generation process to enhance design productivity, while still providing rich customization for efficient area and routing resource utilizations. Process-specific parameterized cells (PCells) are combined with process-independent place-and-route functions to automatically generate area-efficient and programmable layouts. Routing grids are optimized to enhance the area and routing efficiency. The proposed method reduced the design time of digital layouts by 80% compared to a manual design with high layout qualities, significantly enhancing the design productivity.
- URI
- https://ieeexplore.ieee.org/document/9474014https://repository.hanyang.ac.kr/handle/20.500.11754/175890
- DOI
- 10.23919/DATE51398.2021.9474014
- Appears in Collections:
- COLLEGE OF ENGINEERING[S](공과대학) > ELECTRONIC ENGINEERING(융합전자공학부) > Articles
- Files in This Item:
There are no files associated with this item.
- Export
- RIS (EndNote)
- XLS (Excel)
- XML