Full metadata record
DC Field | Value | Language |
---|---|---|
dc.contributor.author | 박성주 | - |
dc.date.accessioned | 2022-08-22T23:57:04Z | - |
dc.date.available | 2022-08-22T23:57:04Z | - |
dc.date.issued | 2021-07 | - |
dc.identifier.citation | IEEE ACCESS, v. 9, Page. 96700-96710 | en_US |
dc.identifier.issn | 2169-3536 | - |
dc.identifier.uri | https://doaj.org/article/4c17aae9c20640678c7c6ef41f7be6eb | - |
dc.identifier.uri | https://repository.hanyang.ac.kr/handle/20.500.11754/172538 | - |
dc.description.abstract | The application diversity and evolution of AI accelerator architectures require innovative DFT solutions to address issues such as test time, test power, performance and area overhead. Full scan DFT, because of its enhanced controllability and observability, is an industrial de facto test strategy. However, it may not yield an optimal test solution with stringent design constraints of edge-based AI accelerators. In this paper, a novel test architecture based on selective-partial scan is proposed for performance, power and area (PPA) overhead constrained edge-based systolic AI accelerator. In this architecture, the structural test patterns are applied partly in functional manner, which reduces the testability problem of an array to that of a single processing element (PE); thus, resulting in reduced test time and test data volume. Moreover, a delay fault testing method based on Launch-on-Capture is presented for the partial scan based proposed architecture. Experimental results show that proposed architecture is efficient in terms of test power and test time when compared to full scan DFT. | en_US |
dc.description.sponsorship | This work was supported in part by the Higher Education Commission, Government of Pakistan, under the Scholarship Program Faculty Development of University of Engineering Science and Technology Pakistan/University of Engineering and Technology (UESTPs/UETs), in part by the BK21 FOUR (Fostering Outstanding Universities for Research) funded by the Ministry of Education (MOE), South Korea, and in part by the National Research Foundation of Korea (NRF). | en_US |
dc.language.iso | en | en_US |
dc.publisher | IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC | en_US |
dc.subject | Design for testability | en_US |
dc.subject | systolic arrays | en_US |
dc.subject | TAM | en_US |
dc.subject | testing | en_US |
dc.title | Test Architecture for Systolic Array of Edge-Based AI Accelerator | en_US |
dc.type | Article | en_US |
dc.relation.volume | 9 | - |
dc.identifier.doi | 10.1109/ACCESS.2021.3094741 | - |
dc.relation.page | 96700-96710 | - |
dc.relation.journal | IEEE ACCESS | - |
dc.contributor.googleauthor | Solangi, Umair Saeed | - |
dc.contributor.googleauthor | Ibtesam, Muhammad | - |
dc.contributor.googleauthor | Ansari, Muhammad Adil | - |
dc.contributor.googleauthor | Kim, Jinuk | - |
dc.contributor.googleauthor | Park, Sungju | - |
dc.relation.code | 2021000011 | - |
dc.sector.campus | E | - |
dc.sector.daehak | COLLEGE OF COMPUTING[E] | - |
dc.sector.department | SCHOOL OF COMPUTER SCIENCE | - |
dc.identifier.pid | paksj | - |
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