A Simulation Study on Impact of Residual Stress on Polysilicon Channel in Scaled 3D NAND Flash Memory

Abstract

The memory market, originally driven solely by the mobile device industry, has expanded because of emerging artificial intelligence and automobiles industries. The explosive growth of data generated by these industries demands an increase in the storage capacity of 3D NAND. This demand has been met by increasing the number of stacking gate layers (WL), which reached 128 levels in 2019 [1,2]. As the number of WL layers increases, the difficulties in fabrication, such as hole etching and control of the mechanical stress, have increased [3,4]. Therefore, vertical scaling is necessary to achieve 3D NAND technology with 200 levels and beyond because the thickness of the total chip is limited to approximately 25 µm for stacking 16 chips [5]. Moreover, lateral scaling of the hole diameter is another way to achieve a higher density [6]. The annealing temperature, channel hole angle, and tungsten intrinsic stress were parameters that change the residual stress of the polysilicon channel in 3D NAND. This change in stress distribution of the polysilicon channel affect the electrical characteristics, degrading the 3D NAND BL current [7]. Furthermore, the residual stress generated the dangling bond, which increases the trap site leading to deterioration of the interface properties. Therefore, cell characteristics, such as the leakage current and memory window, were degraded [8]. In this thesis, the effects of residual stress in a tungsten gate on a polysilicon channel in scaled 3D NAND flash memories were investigated using a technology computer-aided design simulation (TCAD). The NAND strings with respect to the distance from the tungsten slit were also analyzed. The scaling of the spacer thickness and hole diameter induced compressive stress on the polysilicon channel. Moreover, the residual stress of polysilicon channel in the string near the tungsten slit had greater compressive stress than the string farther away. The increase in compressive stress in the polysilicon channel degraded the Bit-Line current (ION) because of stress-induced electron mobility deterioration. Moreover, a threshold voltage shift (∆Vth) occurred in the negative direction because of conduction band lowering.