Full metadata record
DC Field | Value | Language |
---|---|---|
dc.contributor.author | 유창식 | - |
dc.date.accessioned | 2021-12-06T05:12:21Z | - |
dc.date.available | 2021-12-06T05:12:21Z | - |
dc.date.issued | 2020-05 | - |
dc.identifier.citation | IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, v. 28, no. 5, page. 1107-1117 | en_US |
dc.identifier.issn | 1063-8210 | - |
dc.identifier.issn | 1557-9999 | - |
dc.identifier.uri | https://ieeexplore.ieee.org/document/8999809 | - |
dc.identifier.uri | https://repository.hanyang.ac.kr/handle/20.500.11754/166705 | - |
dc.description.abstract | A receiver for a three-lane 6-Gb/s/lane serial link has been developed in 28-nm CMOS technology. It incorporates an intrapair skew compensator (IPSC) and a three-tap decision feedback equalizer (DFE). The IPSC removes the IPS in analog front end by adding differential and common-mode signals of a differential pair. The three-tap DFE is realized with clock and data recovery (CDR) circuit with minimum hardware complexity. The receiver consumes 31.0 mW/lane at 6 Gb/s/lane and occupies an active area of 0.08 mm(2). | en_US |
dc.description.sponsorship | This work was supported in part by the Ministry of Trade, Industry and Energy, South Korea, through the Industrial Technology Innovation Program (IP Development and Standard Definition for 8K/4K Display) under Grant 10080285 and in part by the Future Interconnect Technology Cluster Program of Samsung Electronics, South Korea. | en_US |
dc.language.iso | en | en_US |
dc.publisher | IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC | en_US |
dc.subject | Clock and data recovery (CDR) | en_US |
dc.subject | CMOS | en_US |
dc.subject | decision feedback equalizer (DFE) | en_US |
dc.subject | intrapair skew (IPS) | en_US |
dc.subject | wireline receiver | en_US |
dc.title | A 6-Gb/s Wireline Receiver With Intrapair Skew Compensation and Three-Tap Decision-Feedback Equalizer in 28-nm CMOS | en_US |
dc.type | Article | en_US |
dc.relation.no | 5 | - |
dc.relation.volume | 28 | - |
dc.identifier.doi | 10.1109/TVLSI.2020.2971558 | - |
dc.relation.page | 1107-1117 | - |
dc.relation.journal | IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS | - |
dc.contributor.googleauthor | Kim, Hyochang | - |
dc.contributor.googleauthor | Yoo, Changsik | - |
dc.relation.code | 2020047924 | - |
dc.sector.campus | S | - |
dc.sector.daehak | COLLEGE OF ENGINEERING[S] | - |
dc.sector.department | SCHOOL OF ELECTRONIC ENGINEERING | - |
dc.identifier.pid | csyoo | - |
dc.identifier.orcid | https://orcid.org/0000-0001-7945-5400 | - |
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