Flit-Partitioned Parallel Test Technique for NoC Based SoCs
- Title
- Flit-Partitioned Parallel Test Technique for NoC Based SoCs
- Author
- 박성주
- Keywords
- Network-on-Chip; Multicast of packets
- Issue Date
- 2009-06
- Publisher
- 한국반도체테스트협회
- Citation
- 한국테스트학술대회 2009, 2pp
- Abstract
- 효율적인 NoC 테스트기술 개발, Reusing on-chip functional interconnects as test access mechanism (TAM) appeared natural these days. One of the most important functional interconnects for highly crowded future SoCs is Network-on-Chip (NoC). Till date different kinds of synchronous, asynchronous NoC architectures, router and network interface (NI) architectures have been proposed, to allow multicast of packets, in-order packet delivery, guaranteed throughput and best-effort services. Exploiting these features, we present here a flit-partitioned parallel test technique for NoC based SoCs while reusing NoC as TAM, to reduce the test time.
- URI
- http://www.koreatest.or.kr/sub02/2009data/report/d09-037.pdfhttps://repository.hanyang.ac.kr/handle/20.500.11754/166019
- Appears in Collections:
- ETC[S] > 연구정보
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