Full metadata record
DC Field | Value | Language |
---|---|---|
dc.contributor.author | 박성주 | - |
dc.date.accessioned | 2021-10-29T02:17:20Z | - |
dc.date.available | 2021-10-29T02:17:20Z | - |
dc.date.issued | 2009-06 | - |
dc.identifier.citation | 한국테스트학술대회 2009, 2pp | en_US |
dc.identifier.uri | http://www.koreatest.or.kr/sub02/2009data/report/l09-038.pdf | - |
dc.identifier.uri | https://repository.hanyang.ac.kr/handle/20.500.11754/166018 | - |
dc.description.abstract | 테스트랩퍼를 포함한 기능성팹퍼 제안. With the scalability of SoC (System-on-a-Chip), the complexity and the area overhead of test logic are also increasing. Especially the area overhead of design for testable (DFT) logic including IEEE 1500 std. compliant test wrapper has reached approximately 10% of actual design. This paper introduces a design technique to reuse functional wrapper as IEEE 1500 compliant test wrapper which reduces DFT area overhead significantly. | en_US |
dc.description.sponsorship | 본 연구보고서는 지식경제부 출연금으로 ETRI, 시스템반도체산업진흥센터에서 수행한 IT SoC 핵심설계 인력양성사업의 연구결과입니다. 설계툴은 반도체설계 교육센터(IDEC)의 지원을 받았습니다. | en_US |
dc.language.iso | ko_KR | en_US |
dc.publisher | 한국반도체테스트협회 | en_US |
dc.subject | IEEE 1500 wrapper | en_US |
dc.subject | test wrapper | en_US |
dc.title | 코아의 기능성 래퍼를 IEEE 1500 래퍼로 재사용하기 위한 디자인 기법 | en_US |
dc.title.alternative | A Design Technique to Reuse Functional Wrapper as IEEE 1500 Compliant Test Wrapper | en_US |
dc.type | Article | en_US |
dc.contributor.googleauthor | 황두찬 | - |
dc.contributor.googleauthor | 정혜란 | - |
dc.contributor.googleauthor | 김화영 | - |
dc.contributor.googleauthor | 박성주 | - |
dc.sector.campus | E | - |
dc.sector.daehak | COLLEGE OF COMPUTING[E] | - |
dc.sector.department | DIVISION OF COMPUTER SCIENCE | - |
dc.identifier.pid | paksj | - |
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