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dc.contributor.author김상욱-
dc.date.accessioned2021-10-26T05:57:01Z-
dc.date.available2021-10-26T05:57:01Z-
dc.date.issued2020-04-
dc.identifier.citation2020 IEEE 36th International Conference on Data Engineering (ICDE), page. 925-936en_US
dc.identifier.isbn978-1-7281-2903-7-
dc.identifier.issn2375-026X-
dc.identifier.urihttps://ieeexplore.ieee.org/document/9101654?arnumber=9101654&SID=EBSCO:edseee-
dc.identifier.urihttps://repository.hanyang.ac.kr/handle/20.500.11754/165755-
dc.description.abstractSparse matrix multiplication (spGEMM) is widely used to analyze the sparse network data, and extract important information based on matrix representation. As it contains a high degree of data parallelism, many efficient implementations using data-parallel programming platforms such as CUDA and OpenCL have been introduced on graphic processing units (GPUs). Several well-known spGEMM techniques, such as cuS- PARSE and CUSP, often do not utilize the GPU resources fully, owing to the load imbalance between threads in the expansion process and high memory contention in the merge process. Furthermore, even though several outer-product-based spGEMM techniques are proposed to solve the load balancing problem on expansion, they still do not utilize the GPU resources fully, because severe computation load variations exist among the multiple thread blocks.To solve these challenges, this paper proposes a new optimization pass called Block Reorganizer, which balances the total computations of each computing unit on target GPUs, based on the outer-product-based expansion process, and reduces the memory pressure during the merge process. For expansion, it first identifies the actual computation amount for each block, and then performs two thread block transformation processes based on their characteristics: 1) B-Splitting to transform a heavy-computation blocks into multiple small blocks and 2) B- Gathering to aggregate multiple small-computation blocks to a larger block. While merging, it improves the overall performance by performing B-Limiting to limit the number of blocks on each computing unit. Experimental results show that it improves the total performance of kernel execution by 1.43x, on an average, when compared to the row-product-based spGEMM, for NVIDIA Titan Xp GPUs on real-world datasets.en_US
dc.description.sponsorshipThanks to Myung-Hwan Jang and Hyuck-Moo Gwon for all their help and feedback. We also thank the anonymous reviewers who provided good suggestions for improving the quality of this work. This work was supported by Samsung Research Funding & Incubation Center of Samsung Electronics under Project Number SRFC-IT1901- 03. Yongjun Park is the corresponding author.en_US
dc.language.isoenen_US
dc.publisherIEEE ICDE 2020en_US
dc.subjectSparse matrix multiplicationen_US
dc.subjectsparse networken_US
dc.subjectGPUen_US
dc.subjectlinear algebraen_US
dc.titleOptimization of a GPU-based Sparse Matrix Multiplication for Large Sparse Networksen_US
dc.typeArticleen_US
dc.identifier.doi10.1109/ICDE48307.2020.00085-
dc.relation.page925-936-
dc.contributor.googleauthorLee, Jeongmyung-
dc.contributor.googleauthorKang, Seokwon-
dc.contributor.googleauthorYu, Yongseung-
dc.contributor.googleauthorJo, Yong-Yeon-
dc.contributor.googleauthorKim, Sang-Wook-
dc.contributor.googleauthorPark, Yongjun-
dc.relation.code20200060-
dc.sector.campusS-
dc.sector.daehakCOLLEGE OF ENGINEERING[S]-
dc.sector.departmentSCHOOL OF COMPUTER SCIENCE-
dc.identifier.pidwook-
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COLLEGE OF ENGINEERING[S](공과대학) > COMPUTER SCIENCE(컴퓨터소프트웨어학부) > Articles
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